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[X86] combinePMULH - we can treat constant vectors as freely truncatable.
Fixes #109790
1 parent 9e60a6a commit 406a212

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2 files changed

+9
-29
lines changed

2 files changed

+9
-29
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53022,9 +53022,10 @@ static SDValue combinePMULH(SDValue Src, EVT VT, const SDLoc &DL,
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5302353023
// Check if both inputs are extensions, which will be removed by truncation.
5302453024
auto isOpTruncateFree = [](SDValue Op) {
53025-
return (Op.getOpcode() == ISD::SIGN_EXTEND ||
53026-
Op.getOpcode() == ISD::ZERO_EXTEND) &&
53027-
Op.getOperand(0).getScalarValueSizeInBits() <= 16;
53025+
if (Op.getOpcode() == ISD::SIGN_EXTEND ||
53026+
Op.getOpcode() == ISD::ZERO_EXTEND)
53027+
return Op.getOperand(0).getScalarValueSizeInBits() <= 16;
53028+
return ISD::isBuildVectorOfConstantSDNodes(Op.getNode());
5302853029
};
5302953030
bool IsTruncateFree = isOpTruncateFree(LHS) && isOpTruncateFree(RHS);
5303053031

llvm/test/CodeGen/X86/pmulh.ll

Lines changed: 5 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -974,32 +974,11 @@ define <16 x i16> @zext_mulhuw_v16i16_positive_constant(<16 x i16> %a) {
974974
; SSE-NEXT: pmulhw %xmm2, %xmm1
975975
; SSE-NEXT: retq
976976
;
977-
; AVX2-LABEL: zext_mulhuw_v16i16_positive_constant:
978-
; AVX2: # %bb.0:
979-
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
980-
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
981-
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
982-
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
983-
; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0]
984-
; AVX2-NEXT: vpmulhuw %ymm2, %ymm0, %ymm0
985-
; AVX2-NEXT: vpmulhuw %ymm2, %ymm1, %ymm1
986-
; AVX2-NEXT: vpackusdw %ymm0, %ymm1, %ymm0
987-
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
988-
; AVX2-NEXT: retq
989-
;
990-
; AVX512F-LABEL: zext_mulhuw_v16i16_positive_constant:
991-
; AVX512F: # %bb.0:
992-
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
993-
; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000]
994-
; AVX512F-NEXT: retq
995-
;
996-
; AVX512BW-LABEL: zext_mulhuw_v16i16_positive_constant:
997-
; AVX512BW: # %bb.0:
998-
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
999-
; AVX512BW-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
1000-
; AVX512BW-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0,1000,0]
1001-
; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0
1002-
; AVX512BW-NEXT: retq
977+
; AVX-LABEL: zext_mulhuw_v16i16_positive_constant:
978+
; AVX: # %bb.0:
979+
; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
980+
; AVX-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000,1000]
981+
; AVX-NEXT: retq
1003982
%k = and <16 x i16> %a, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>
1004983
%x = zext nneg <16 x i16> %k to <16 x i32>
1005984
%m = mul nuw nsw <16 x i32> %x, <i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000, i32 1000>

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