@@ -30,9 +30,6 @@ using namespace llvm;
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namespace {
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class AArch64AsmBackend : public MCAsmBackend {
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- static const unsigned PCRelFlagVal =
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- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
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-
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protected:
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Triple TheTriple;
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@@ -51,22 +48,22 @@ class AArch64AsmBackend : public MCAsmBackend {
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// in AArch64FixupKinds.h.
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//
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// Name Offset (bits) Size (bits) Flags
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- {" fixup_aarch64_pcrel_adr_imm21" , 0 , 32 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_adrp_imm21" , 0 , 32 , PCRelFlagVal },
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+ {" fixup_aarch64_pcrel_adr_imm21" , 0 , 32 , 0 },
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+ {" fixup_aarch64_pcrel_adrp_imm21" , 0 , 32 , 0 },
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{" fixup_aarch64_add_imm12" , 10 , 12 , 0 },
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{" fixup_aarch64_ldst_imm12_scale1" , 10 , 12 , 0 },
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{" fixup_aarch64_ldst_imm12_scale2" , 10 , 12 , 0 },
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{" fixup_aarch64_ldst_imm12_scale4" , 10 , 12 , 0 },
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{" fixup_aarch64_ldst_imm12_scale8" , 10 , 12 , 0 },
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{" fixup_aarch64_ldst_imm12_scale16" , 10 , 12 , 0 },
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- {" fixup_aarch64_ldr_pcrel_imm19" , 5 , 19 , PCRelFlagVal },
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+ {" fixup_aarch64_ldr_pcrel_imm19" , 5 , 19 , 0 },
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{" fixup_aarch64_movw" , 5 , 16 , 0 },
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- {" fixup_aarch64_pcrel_branch9" , 5 , 9 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_branch14" , 5 , 14 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_branch16" , 5 , 16 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_branch19" , 5 , 19 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_branch26" , 0 , 26 , PCRelFlagVal },
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- {" fixup_aarch64_pcrel_call26" , 0 , 26 , PCRelFlagVal }};
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+ {" fixup_aarch64_pcrel_branch9" , 5 , 9 , 0 },
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+ {" fixup_aarch64_pcrel_branch14" , 5 , 14 , 0 },
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+ {" fixup_aarch64_pcrel_branch16" , 5 , 16 , 0 },
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+ {" fixup_aarch64_pcrel_branch19" , 5 , 19 , 0 },
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+ {" fixup_aarch64_pcrel_branch26" , 0 , 26 , 0 },
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+ {" fixup_aarch64_pcrel_call26" , 0 , 26 , 0 }};
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// Fixup kinds from raw relocation types and .reloc directives force
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// relocations and do not need these fields.
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