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[Xtensa] Implement THREADPTR and DFPAccel Xtensa Options. (#145543)
Implment base support of the TLS functionality using Xtensa THREADPTR Option. Implement basic functionality of the DFPAccel Option(registers support).
1 parent 2dc44b3 commit 3dc09fb

16 files changed

+255
-8
lines changed

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
//
99
//===----------------------------------------------------------------------===//
1010

11+
#include "MCTargetDesc/XtensaMCExpr.h"
1112
#include "MCTargetDesc/XtensaMCTargetDesc.h"
1213
#include "llvm/ADT/STLExtras.h"
1314
#include "llvm/BinaryFormat/ELF.h"
@@ -45,10 +46,12 @@ XtensaObjectWriter::~XtensaObjectWriter() {}
4546
unsigned XtensaObjectWriter::getRelocType(const MCFixup &Fixup,
4647
const MCValue &Target,
4748
bool IsPCRel) const {
49+
uint8_t Specifier = Target.getSpecifier();
4850

4951
switch ((unsigned)Fixup.getKind()) {
5052
case FK_Data_4:
51-
return ELF::R_XTENSA_32;
53+
return Specifier == Xtensa::S_TPOFF ? ELF::R_XTENSA_TLS_TPOFF
54+
: ELF::R_XTENSA_32;
5255
default:
5356
return ELF::R_XTENSA_SLOT0_OP;
5457
}

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -186,11 +186,17 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
186186
return FeatureBits[Xtensa::FeatureMiscSR];
187187
case Xtensa::PRID:
188188
return RAType == Xtensa::REGISTER_READ && FeatureBits[Xtensa::FeaturePRID];
189+
case Xtensa::THREADPTR:
190+
return FeatureBits[FeatureTHREADPTR];
189191
case Xtensa::VECBASE:
190192
return FeatureBits[Xtensa::FeatureRelocatableVector];
191193
case Xtensa::FCR:
192194
case Xtensa::FSR:
193195
return FeatureBits[FeatureSingleFloat];
196+
case Xtensa::F64R_LO:
197+
case Xtensa::F64R_HI:
198+
case Xtensa::F64S:
199+
return FeatureBits[FeatureDFPAccel];
194200
case Xtensa::WINDOWBASE:
195201
case Xtensa::WINDOWSTART:
196202
return FeatureBits[Xtensa::FeatureWindowed];
@@ -203,12 +209,23 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
203209

204210
// Get Xtensa User Register by encoding value.
205211
MCRegister Xtensa::getUserRegister(unsigned Code, const MCRegisterInfo &MRI) {
212+
MCRegister UserReg = Xtensa::NoRegister;
213+
206214
if (MRI.getEncodingValue(Xtensa::FCR) == Code) {
207-
return Xtensa::FCR;
215+
UserReg = Xtensa::FCR;
208216
} else if (MRI.getEncodingValue(Xtensa::FSR) == Code) {
209-
return Xtensa::FSR;
217+
UserReg = Xtensa::FSR;
218+
} else if (MRI.getEncodingValue(Xtensa::F64R_LO) == Code) {
219+
UserReg = Xtensa::F64R_LO;
220+
} else if (MRI.getEncodingValue(Xtensa::F64R_HI) == Code) {
221+
UserReg = Xtensa::F64R_HI;
222+
} else if (MRI.getEncodingValue(Xtensa::F64S) == Code) {
223+
UserReg = Xtensa::F64S;
224+
} else if (MRI.getEncodingValue(Xtensa::THREADPTR) == Code) {
225+
UserReg = Xtensa::THREADPTR;
210226
}
211-
return Xtensa::NoRegister;
227+
228+
return UserReg;
212229
}
213230

214231
static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,

‎llvm/lib/Target/Xtensa/XtensaFeatures.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,11 @@ def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
9898
def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
9999
AssemblerPredicate<(all_of FeatureDataCache)>;
100100

101+
def FeatureTHREADPTR : SubtargetFeature<"threadptr", "HasTHREADPTR", "true",
102+
"Enable Xtensa THREADPTR option">;
103+
def HasTHREADPTR : Predicate<"Subtarget->hasTHREADPTR()">,
104+
AssemblerPredicate<(all_of FeatureTHREADPTR)>;
105+
101106
// Xtensa Interrupts Options.
102107
def FeatureHighPriInterrupts : SubtargetFeature<"highpriinterrupts",
103108
"HasHighPriInterrupts", "true",
@@ -137,3 +142,8 @@ def FeatureCoprocessor : SubtargetFeature<"coprocessor", "HasCoprocessor", "true
137142
"Enable Xtensa Coprocessor option">;
138143
def HasCoprocessor : Predicate<"Subtarget->hasCoprocessor()">,
139144
AssemblerPredicate<(all_of FeatureCoprocessor)>;
145+
146+
def FeatureDFPAccel : SubtargetFeature<"dfpaccel", "HasDFPAccel", "true",
147+
"Enable Xtensa Double Precision FP acceleration">;
148+
def HasDFPAccel : Predicate<"Subtarget->hasDFPAccel()">,
149+
AssemblerPredicate<(all_of FeatureDFPAccel)>;

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
101101

102102
setOperationAction(ISD::ConstantPool, PtrVT, Custom);
103103
setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
104+
setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
104105
setOperationAction(ISD::BlockAddress, PtrVT, Custom);
105106
setOperationAction(ISD::JumpTable, PtrVT, Custom);
106107

@@ -972,6 +973,58 @@ SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op,
972973
return Res;
973974
}
974975

976+
SDValue XtensaTargetLowering::LowerGlobalTLSAddress(SDValue Op,
977+
SelectionDAG &DAG) const {
978+
const GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
979+
SDLoc DL(Op);
980+
EVT PtrVT = Op.getValueType();
981+
const GlobalValue *GV = G->getGlobal();
982+
983+
if (DAG.getTarget().useEmulatedTLS())
984+
return LowerToTLSEmulatedModel(G, DAG);
985+
986+
TLSModel::Model model = getTargetMachine().getTLSModel(GV);
987+
988+
if (!Subtarget.hasTHREADPTR()) {
989+
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
990+
DAG.getMachineFunction().getFunction(), "only emulated TLS supported",
991+
DL.getDebugLoc()));
992+
return DAG.getPOISON(Op->getValueType(0));
993+
}
994+
995+
if (model == TLSModel::LocalExec || model == TLSModel::InitialExec) {
996+
bool Priv = GV->isPrivateLinkage(GV->getLinkage());
997+
MachineFunction &MF = DAG.getMachineFunction();
998+
XtensaMachineFunctionInfo *XtensaFI =
999+
MF.getInfo<XtensaMachineFunctionInfo>();
1000+
unsigned LabelId = XtensaFI->createCPLabelId();
1001+
1002+
// Create a constant pool entry for the callee address
1003+
XtensaConstantPoolValue *CPV = XtensaConstantPoolSymbol::Create(
1004+
*DAG.getContext(), GV->getName().str().c_str(), LabelId, Priv,
1005+
XtensaCP::TPOFF);
1006+
1007+
// Get the address of the callee into a register
1008+
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
1009+
SDValue CPWrap = getAddrPCRel(CPAddr, DAG);
1010+
SDValue Addr = DAG.getLoad(
1011+
PtrVT, DL, DAG.getEntryNode(), CPWrap,
1012+
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
1013+
1014+
SDValue TPRegister = DAG.getRegister(Xtensa::THREADPTR, MVT::i32);
1015+
SDValue ThreadPointer =
1016+
DAG.getNode(XtensaISD::RUR, DL, MVT::i32, TPRegister);
1017+
1018+
return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Addr);
1019+
}
1020+
1021+
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
1022+
DAG.getMachineFunction().getFunction(),
1023+
"only local-exec and initial-exec TLS mode supported", DL.getDebugLoc()));
1024+
1025+
return DAG.getPOISON(Op->getValueType(0));
1026+
}
1027+
9751028
SDValue XtensaTargetLowering::LowerBlockAddress(SDValue Op,
9761029
SelectionDAG &DAG) const {
9771030
BlockAddressSDNode *Node = cast<BlockAddressSDNode>(Op);
@@ -1406,6 +1459,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
14061459
return LowerRETURNADDR(Op, DAG);
14071460
case ISD::GlobalAddress:
14081461
return LowerGlobalAddress(Op, DAG);
1462+
case ISD::GlobalTLSAddress:
1463+
return LowerGlobalTLSAddress(Op, DAG);
14091464
case ISD::BlockAddress:
14101465
return LowerBlockAddress(Op, DAG);
14111466
case ISD::JumpTable:
@@ -1459,6 +1514,8 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
14591514
return "XtensaISD::RET";
14601515
case XtensaISD::RETW:
14611516
return "XtensaISD::RETW";
1517+
case XtensaISD::RUR:
1518+
return "XtensaISD::RUR";
14621519
case XtensaISD::SELECT_CC:
14631520
return "XtensaISD::SELECT_CC";
14641521
case XtensaISD::SELECT_CC_FP:

‎llvm/lib/Target/Xtensa/XtensaISelLowering.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,8 @@ enum {
4545
RET,
4646
RETW,
4747

48+
RUR,
49+
4850
// Select with condition operator - This selects between a true value and
4951
// a false value (ops #2 and #3) based on the boolean result of comparing
5052
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
@@ -161,6 +163,8 @@ class XtensaTargetLowering : public TargetLowering {
161163

162164
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
163165

166+
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
167+
164168
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
165169

166170
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -575,7 +575,7 @@ def WUR : RRR_Inst<0x00, 0x03, 0x0F, (outs UR:$ur), (ins AR:$t),
575575
}
576576

577577
def RUR : RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur),
578-
"rur\t$r, $ur", []> {
578+
"rur\t$r, $ur", [(set AR:$r, (Xtensa_rur UR:$ur))]> {
579579
bits<8> ur;
580580

581581
let s = ur{7-4};

‎llvm/lib/Target/Xtensa/XtensaOperators.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,8 @@ def SDT_XtensaEXTUI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCi
3939

4040
def SDT_XtensaMOVSP : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4141

42+
def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
43+
4244
//===----------------------------------------------------------------------===//
4345
// Node definitions
4446
//===----------------------------------------------------------------------===//
@@ -77,6 +79,9 @@ def Xtensa_extui: SDNode<"XtensaISD::EXTUI", SDT_XtensaEXTUI>;
7779
def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP,
7880
[SDNPHasChain, SDNPSideEffect, SDNPInGlue]>;
7981

82+
def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR,
83+
[SDNPInGlue]>;
84+
8085
def Xtensa_cmpoeq : SDNode<"XtensaISD::CMPOEQ", SDT_XtensaCmp, [SDNPOutGlue]>;
8186
def Xtensa_cmpolt : SDNode<"XtensaISD::CMPOLT", SDT_XtensaCmp, [SDNPOutGlue]>;
8287
def Xtensa_cmpole : SDNode<"XtensaISD::CMPOLE", SDT_XtensaCmp, [SDNPOutGlue]>;

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,10 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
5353
// Reserve frame pointer.
5454
Reserved.set(getFrameRegister(MF));
5555
}
56-
56+
if (Subtarget.hasTHREADPTR()) {
57+
// Reserve frame pointer.
58+
Reserved.set(Xtensa::THREADPTR);
59+
}
5760
// Reserve stack pointer.
5861
Reserved.set(Xtensa::SP);
5962
return Reserved;

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.td

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,10 +234,19 @@ class URReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {
234234
let AltNames = alt;
235235
}
236236

237+
// Thread Pointer register
238+
def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>;
239+
237240
def FCR : URReg<232, "fcr", ["FCR"]>;
238241
def FSR : URReg<233, "fsr", ["FSR"]>;
239242

240-
def UR : RegisterClass<"Xtensa", [i32], 32, (add FCR, FSR)>;
243+
// DFPAccel registers
244+
def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>;
245+
def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>;
246+
def F64S : URReg<236, "f64s", ["F64S"]>;
247+
248+
def UR : RegisterClass<"Xtensa", [i32], 32, (add
249+
THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S)>;
241250

242251
//===----------------------------------------------------------------------===//
243252
// Floating-Point registers

‎llvm/lib/Target/Xtensa/XtensaSubtarget.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
9191
bool hasHighPriInterruptsLevel7() const { return HasHighPriInterruptsLevel7; }
9292
bool hasInterrupt() const { return HasInterrupt; }
9393
bool hasException() const { return HasException; }
94-
94+
bool hasTHREADPTR() const { return HasTHREADPTR; }
9595
bool isWindowedABI() const { return hasWindowed(); }
9696

9797
// Automatically generated by tblgen.

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