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+279
-192
lines changed

8 files changed

+279
-192
lines changed

‎llvm/include/llvm/Target/Target.td

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,6 +1137,15 @@ class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
11371137
let MIOperandInfo = OpTypes;
11381138
}
11391139

1140+
// InstrDecoderOption - This class is used to provide some options to the
1141+
// TableGen DecoderEmitter backend.
1142+
class InstrDecoderOption<string ty, list<int> bws> {
1143+
string CPPType = ty; // C++ type for generating non-templated code.
1144+
list<int> Bitwidths = bws; // List of bitwidths supported by the above type.
1145+
1146+
assert !not(!empty(CPPType)), "CPP type cannot be empty";
1147+
assert !not(!empty(Bitwidths)), "Bitwidths cannot be empty";
1148+
}
11401149

11411150
// InstrInfo - This class should only be instantiated once to provide parameters
11421151
// which are global to the target machine.
@@ -1159,24 +1168,16 @@ class InstrInfo {
11591168
// This option is a temporary migration help. It will go away.
11601169
bit guessInstructionProperties = true;
11611170

1162-
// These properties, when set, opt into the non-templated variants of
1163-
// `decodeToMCInst` generated by TableGen DecoderEmitter backend. Using this
1164-
// option helps reduce the code size of the generated code as compared to the
1165-
// templated `decodeToMCInst` that is generated by default.
1166-
// For each index `I`, InsnCPPTypes[I] is a C++ type that will be used to
1167-
// generate a non-templated `decodeToMCInst`, and InstBitwidths[I] is a list
1168-
// instruction bitwidth(s) whose decoders will be included in the generated
1169-
// code.
1170-
list<string> InsnCPPTypes = [];
1171-
list<list<int>> InsnBitwidths = [];
1172-
assert !eq(!size(InsnCPPTypes), !size(InsnBitwidths)),
1173-
"The InsnCPPTypes and InsnBitwidths lists must be the same length";
1174-
1175-
// Make sure the InstCPPTypes, if not empty, does not contain empty strings.
1176-
assert !or(!empty(InsnCPPTypes), !empty(!filter(e, InsnCPPTypes, !empty(e)))),
1177-
"Entries in InstCPPTypes cannot be empty";
1178-
1179-
// Make sure that InsnBitwidths, if not empty, does not contain empty list.
1171+
// This is a list of instruction decoder options for this target. When non
1172+
// empty, it should list all the C++ types and associated bitwidths that this
1173+
// target intends to use to call the TableGen generated `decodeInstruction`
1174+
// function. If this list is empty, the decoder emitter will generate
1175+
// templated code. However, if a target intends to call this function with
1176+
// more than one `InsnType`, it may be beneficial to provide these decoder
1177+
// options to generate non-templated form of `decodeInstruction` and
1178+
// associated helper functions and avoid some code duplication in the
1179+
// `decodeToMCInst` function.
1180+
list<InstrDecoderOption> DecoderOptions = [];
11801181
}
11811182

11821183
// Standard Pseudo Instructions.

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,7 @@ include "AArch64SchedPredExynos.td"
4040
include "AArch64SchedPredNeoverse.td"
4141
include "AArch64Combine.td"
4242

43-
def AArch64InstrInfo : InstrInfo {
44-
// Opt-in into non-templated code for instruction decoder.
45-
let InsnCPPTypes = ["uint32_t"];
46-
let InsnBitwidths = [[32]];
47-
}
43+
def AArch64InstrInfo : InstrInfo;
4844

4945
//===----------------------------------------------------------------------===//
5046
// Named operands for MRS/MSR/TLBI/...

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1973,6 +1973,13 @@ def FeatureISAVersion12_Generic: FeatureSet<
19731973

19741974
def AMDGPUInstrInfo : InstrInfo {
19751975
let guessInstructionProperties = 1;
1976+
1977+
// Opt-in into non-templated code for instruction decoder.
1978+
let DecoderOptions = [
1979+
InstrDecoderOption<"uint32_t", [32]>,
1980+
InstrDecoderOption<"uint64_t", [64]>,
1981+
InstrDecoderOption<"DecoderUInt128", [96, 128]>,
1982+
];
19761983
}
19771984

19781985
def AMDGPUAsmParser : AsmParser {

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -591,7 +591,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
591591

592592
// Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
593593
// encodings
594-
if (isGFX11Plus() && Bytes.size() >= 12 ) {
594+
if (isGFX11Plus() && Bytes.size() >= 12) {
595595
DecoderUInt128 DecW = eat12Bytes(Bytes);
596596

597597
if (isGFX11() &&

‎llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,13 +111,13 @@ static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
111111
}
112112
#define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
113113

114-
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
114+
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, const APInt &Insn,
115115
uint64_t Address,
116116
const void *Decoder) {
117117
llvm_unreachable("unimplemented");
118118
}
119119

120-
static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn,
120+
static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, const APInt &Insn,
121121
uint64_t Address,
122122
const void *Decoder) {
123123
llvm_unreachable("unimplemented");

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,10 +85,6 @@ include "RISCVPfmCounters.td"
8585

8686
def RISCVInstrInfo : InstrInfo {
8787
let guessInstructionProperties = 0;
88-
89-
// Opt-in into non-templated code for instruction decoder.
90-
let InsnCPPTypes = ["uint64_t"];
91-
let InsnBitwidths = [[16, 32, 48]];
9288
}
9389

9490
def RISCVAsmParser : AsmParser {

‎llvm/test/CMakeLists.txt

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -62,70 +62,70 @@ configure_lit_site_cfg(
6262
set(LLVM_TEST_DEPENDS
6363
BugpointPasses
6464
FileCheck
65-
LLVMWindowsDriver
66-
UnitTests
67-
bugpoint
65+
#LLVMWindowsDriver
66+
#UnitTests
67+
#bugpoint
6868
count
69-
llc
70-
lli
71-
lli-child-target
72-
llvm-addr2line
73-
llvm-ar
74-
llvm-as
75-
llvm-bcanalyzer
76-
llvm-bitcode-strip
77-
llvm-c-test
78-
llvm-cat
79-
llvm-cfi-verify
80-
llvm-cgdata
69+
#llc
70+
#lli
71+
#lli-child-target
72+
#llvm-addr2line
73+
#llvm-ar
74+
#llvm-as
75+
#llvm-bcanalyzer
76+
#llvm-bitcode-strip
77+
#llvm-c-test
78+
#llvm-cat
79+
#llvm-cfi-verify
80+
#llvm-cgdata
8181
llvm-config
82-
llvm-cov
83-
llvm-ctxprof-util
84-
llvm-cvtres
85-
llvm-cxxdump
86-
llvm-cxxfilt
87-
llvm-cxxmap
88-
llvm-debuginfo-analyzer
89-
llvm-debuginfod-find
90-
llvm-diff
82+
#llvm-cov
83+
#llvm-ctxprof-util
84+
#llvm-cvtres
85+
#llvm-cxxdump
86+
#llvm-cxxfilt
87+
#llvm-cxxmap
88+
#llvm-debuginfo-analyzer
89+
#llvm-debuginfod-find
90+
#llvm-diff
9191
llvm-dis
92-
llvm-dlltool
93-
dsymutil
94-
llvm-dwarfdump
95-
llvm-dwarfutil
96-
llvm-dwp
97-
llvm-exegesis
98-
llvm-extract
99-
llvm-gsymutil
100-
llvm-isel-fuzzer
101-
llvm-ifs
92+
#llvm-dlltool
93+
#dsymutil
94+
#llvm-dwarfdump
95+
#llvm-dwarfutil
96+
#llvm-dwp
97+
#llvm-exegesis
98+
#llvm-extract
99+
#llvm-gsymutil
100+
#llvm-isel-fuzzer
101+
#llvm-ifs
102102
llvm-install-name-tool
103-
llvm-jitlink
104-
llvm-lib
105-
llvm-libtool-darwin
106-
llvm-link
107-
llvm-lipo
108-
llvm-locstats
109-
llvm-lto2
103+
#llvm-jitlink
104+
#llvm-lib
105+
#llvm-libtool-darwin
106+
#llvm-link
107+
#llvm-lipo
108+
#llvm-locstats
109+
#llvm-lto2
110110
llvm-mc
111111
llvm-mca
112-
llvm-ml
113-
llvm-ml64
114-
llvm-modextract
112+
#llvm-ml
113+
#llvm-ml64
114+
#llvm-modextract
115115
llvm-nm
116116
llvm-objcopy
117117
llvm-objdump
118-
llvm-opt-fuzzer
119-
llvm-opt-report
118+
#llvm-opt-fuzzer
119+
#llvm-opt-report
120120
llvm-otool
121-
llvm-pdbutil
122-
llvm-profdata
123-
llvm-profgen
124-
llvm-ranlib
125-
llvm-rc
121+
#llvm-pdbutil
122+
#llvm-profdata
123+
#llvm-profgen
124+
#llvm-ranlib
125+
#llvm-rc
126126
llvm-readobj
127127
llvm-readelf
128-
llvm-reduce
128+
#llvm-reduce
129129
llvm-remarkutil
130130
llvm-rtdyld
131131
llvm-sim
@@ -143,7 +143,7 @@ set(LLVM_TEST_DEPENDS
143143
llvm-xray
144144
not
145145
obj2yaml
146-
opt
146+
#opt
147147
sancov
148148
sanstats
149149
split-file
@@ -153,11 +153,11 @@ set(LLVM_TEST_DEPENDS
153153
)
154154

155155
if(TARGET llvm-lto)
156-
set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-lto)
156+
#set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-lto)
157157
endif()
158158

159159
if(TARGET llvm-driver)
160-
set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-driver)
160+
#set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-driver)
161161
endif()
162162

163163
# If Intel JIT events are supported, depend on a tool that tests the listener.
@@ -166,15 +166,15 @@ if( LLVM_USE_INTEL_JITEVENTS )
166166
endif( LLVM_USE_INTEL_JITEVENTS )
167167

168168
if(TARGET LLVMgold)
169-
set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LLVMgold)
169+
#set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LLVMgold)
170170
endif()
171171

172172
if(TARGET LTO)
173-
set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LTO)
173+
#set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LTO)
174174
endif()
175175

176176
if (TARGET llvm-mt)
177-
list(APPEND LLVM_TEST_DEPENDS llvm-mt)
177+
#list(APPEND LLVM_TEST_DEPENDS llvm-mt)
178178
endif ()
179179

180180
if(LLVM_BUILD_EXAMPLES)

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