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[RISCV] Convert the XAndesVSIntLoad intrinsic tests to opaque pointers. NFC
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‎llvm/test/CodeGen/RISCV/rvv/xandesvsinload-vln8.ll

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvsintload \
55
; RUN: -verify-machineinstrs -target-abi=lp64 | FileCheck %s
66

7-
define <vscale x 1 x i8> @intrinsic_nds_vln_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, iXLen %1) nounwind {
7+
define <vscale x 1 x i8> @intrinsic_nds_vln_v_nxv1i8_nxv1i8(ptr %0, iXLen %1) nounwind {
88
; CHECK-LABEL: intrinsic_nds_vln_v_nxv1i8_nxv1i8:
99
; CHECK: # %bb.0: # %entry
1010
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
@@ -13,13 +13,13 @@ define <vscale x 1 x i8> @intrinsic_nds_vln_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %
1313
entry:
1414
%a = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8(
1515
<vscale x 1 x i8> poison,
16-
<vscale x 1 x i8>* %0,
16+
ptr %0,
1717
iXLen %1)
1818

1919
ret <vscale x 1 x i8> %a
2020
}
2121

22-
define <vscale x 1 x i8> @intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
22+
define <vscale x 1 x i8> @intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
2323
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8:
2424
; CHECK: # %bb.0: # %entry
2525
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -28,14 +28,14 @@ define <vscale x 1 x i8> @intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i
2828
entry:
2929
%a = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8(
3030
<vscale x 1 x i8> %0,
31-
<vscale x 1 x i8>* %1,
31+
ptr %1,
3232
<vscale x 1 x i1> %2,
3333
iXLen %3, iXLen 1)
3434

3535
ret <vscale x 1 x i8> %a
3636
}
3737

38-
define <vscale x 2 x i8> @intrinsic_nds_vln_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, iXLen %1) nounwind {
38+
define <vscale x 2 x i8> @intrinsic_nds_vln_v_nxv2i8_nxv2i8(ptr %0, iXLen %1) nounwind {
3939
; CHECK-LABEL: intrinsic_nds_vln_v_nxv2i8_nxv2i8:
4040
; CHECK: # %bb.0: # %entry
4141
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
@@ -44,13 +44,13 @@ define <vscale x 2 x i8> @intrinsic_nds_vln_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %
4444
entry:
4545
%a = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8(
4646
<vscale x 2 x i8> poison,
47-
<vscale x 2 x i8>* %0,
47+
ptr %0,
4848
iXLen %1)
4949

5050
ret <vscale x 2 x i8> %a
5151
}
5252

53-
define <vscale x 2 x i8> @intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
53+
define <vscale x 2 x i8> @intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
5454
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8:
5555
; CHECK: # %bb.0: # %entry
5656
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -59,14 +59,14 @@ define <vscale x 2 x i8> @intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i
5959
entry:
6060
%a = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8(
6161
<vscale x 2 x i8> %0,
62-
<vscale x 2 x i8>* %1,
62+
ptr %1,
6363
<vscale x 2 x i1> %2,
6464
iXLen %3, iXLen 1)
6565

6666
ret <vscale x 2 x i8> %a
6767
}
6868

69-
define <vscale x 4 x i8> @intrinsic_nds_vln_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, iXLen %1) nounwind {
69+
define <vscale x 4 x i8> @intrinsic_nds_vln_v_nxv4i8_nxv4i8(ptr %0, iXLen %1) nounwind {
7070
; CHECK-LABEL: intrinsic_nds_vln_v_nxv4i8_nxv4i8:
7171
; CHECK: # %bb.0: # %entry
7272
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
@@ -75,13 +75,13 @@ define <vscale x 4 x i8> @intrinsic_nds_vln_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %
7575
entry:
7676
%a = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8(
7777
<vscale x 4 x i8> poison,
78-
<vscale x 4 x i8>* %0,
78+
ptr %0,
7979
iXLen %1)
8080

8181
ret <vscale x 4 x i8> %a
8282
}
8383

84-
define <vscale x 4 x i8> @intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
84+
define <vscale x 4 x i8> @intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
8585
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8:
8686
; CHECK: # %bb.0: # %entry
8787
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -90,14 +90,14 @@ define <vscale x 4 x i8> @intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i
9090
entry:
9191
%a = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8(
9292
<vscale x 4 x i8> %0,
93-
<vscale x 4 x i8>* %1,
93+
ptr %1,
9494
<vscale x 4 x i1> %2,
9595
iXLen %3, iXLen 1)
9696

9797
ret <vscale x 4 x i8> %a
9898
}
9999

100-
define <vscale x 8 x i8> @intrinsic_nds_vln_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, iXLen %1) nounwind {
100+
define <vscale x 8 x i8> @intrinsic_nds_vln_v_nxv8i8_nxv8i8(ptr %0, iXLen %1) nounwind {
101101
; CHECK-LABEL: intrinsic_nds_vln_v_nxv8i8_nxv8i8:
102102
; CHECK: # %bb.0: # %entry
103103
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
@@ -106,13 +106,13 @@ define <vscale x 8 x i8> @intrinsic_nds_vln_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %
106106
entry:
107107
%a = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8(
108108
<vscale x 8 x i8> poison,
109-
<vscale x 8 x i8>* %0,
109+
ptr %0,
110110
iXLen %1)
111111

112112
ret <vscale x 8 x i8> %a
113113
}
114114

115-
define <vscale x 8 x i8> @intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
115+
define <vscale x 8 x i8> @intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
116116
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8:
117117
; CHECK: # %bb.0: # %entry
118118
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -121,14 +121,14 @@ define <vscale x 8 x i8> @intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i
121121
entry:
122122
%a = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8(
123123
<vscale x 8 x i8> %0,
124-
<vscale x 8 x i8>* %1,
124+
ptr %1,
125125
<vscale x 8 x i1> %2,
126126
iXLen %3, iXLen 1)
127127

128128
ret <vscale x 8 x i8> %a
129129
}
130130

131-
define <vscale x 16 x i8> @intrinsic_nds_vln_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, iXLen %1) nounwind {
131+
define <vscale x 16 x i8> @intrinsic_nds_vln_v_nxv16i8_nxv16i8(ptr %0, iXLen %1) nounwind {
132132
; CHECK-LABEL: intrinsic_nds_vln_v_nxv16i8_nxv16i8:
133133
; CHECK: # %bb.0: # %entry
134134
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -137,13 +137,13 @@ define <vscale x 16 x i8> @intrinsic_nds_vln_v_nxv16i8_nxv16i8(<vscale x 16 x i8
137137
entry:
138138
%a = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8(
139139
<vscale x 16 x i8> poison,
140-
<vscale x 16 x i8>* %0,
140+
ptr %0,
141141
iXLen %1)
142142

143143
ret <vscale x 16 x i8> %a
144144
}
145145

146-
define <vscale x 16 x i8> @intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
146+
define <vscale x 16 x i8> @intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
147147
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8:
148148
; CHECK: # %bb.0: # %entry
149149
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -152,14 +152,14 @@ define <vscale x 16 x i8> @intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8(<vscale x 16
152152
entry:
153153
%a = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8(
154154
<vscale x 16 x i8> %0,
155-
<vscale x 16 x i8>* %1,
155+
ptr %1,
156156
<vscale x 16 x i1> %2,
157157
iXLen %3, iXLen 1)
158158

159159
ret <vscale x 16 x i8> %a
160160
}
161161

162-
define <vscale x 32 x i8> @intrinsic_nds_vln_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, iXLen %1) nounwind {
162+
define <vscale x 32 x i8> @intrinsic_nds_vln_v_nxv32i8_nxv32i8(ptr %0, iXLen %1) nounwind {
163163
; CHECK-LABEL: intrinsic_nds_vln_v_nxv32i8_nxv32i8:
164164
; CHECK: # %bb.0: # %entry
165165
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
@@ -168,13 +168,13 @@ define <vscale x 32 x i8> @intrinsic_nds_vln_v_nxv32i8_nxv32i8(<vscale x 32 x i8
168168
entry:
169169
%a = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8(
170170
<vscale x 32 x i8> poison,
171-
<vscale x 32 x i8>* %0,
171+
ptr %0,
172172
iXLen %1)
173173

174174
ret <vscale x 32 x i8> %a
175175
}
176176

177-
define <vscale x 32 x i8> @intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
177+
define <vscale x 32 x i8> @intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
178178
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8:
179179
; CHECK: # %bb.0: # %entry
180180
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -183,14 +183,14 @@ define <vscale x 32 x i8> @intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8(<vscale x 32
183183
entry:
184184
%a = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8(
185185
<vscale x 32 x i8> %0,
186-
<vscale x 32 x i8>* %1,
186+
ptr %1,
187187
<vscale x 32 x i1> %2,
188188
iXLen %3, iXLen 1)
189189

190190
ret <vscale x 32 x i8> %a
191191
}
192192

193-
define <vscale x 64 x i8> @intrinsic_nds_vln_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, iXLen %1) nounwind {
193+
define <vscale x 64 x i8> @intrinsic_nds_vln_v_nxv64i8_nxv64i8(ptr %0, iXLen %1) nounwind {
194194
; CHECK-LABEL: intrinsic_nds_vln_v_nxv64i8_nxv64i8:
195195
; CHECK: # %bb.0: # %entry
196196
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -199,13 +199,13 @@ define <vscale x 64 x i8> @intrinsic_nds_vln_v_nxv64i8_nxv64i8(<vscale x 64 x i8
199199
entry:
200200
%a = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8(
201201
<vscale x 64 x i8> poison,
202-
<vscale x 64 x i8>* %0,
202+
ptr %0,
203203
iXLen %1)
204204

205205
ret <vscale x 64 x i8> %a
206206
}
207207

208-
define <vscale x 64 x i8> @intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
208+
define <vscale x 64 x i8> @intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
209209
; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8:
210210
; CHECK: # %bb.0: # %entry
211211
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -214,7 +214,7 @@ define <vscale x 64 x i8> @intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8(<vscale x 64
214214
entry:
215215
%a = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8(
216216
<vscale x 64 x i8> %0,
217-
<vscale x 64 x i8>* %1,
217+
ptr %1,
218218
<vscale x 64 x i1> %2,
219219
iXLen %3, iXLen 1)
220220

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