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VyacheslavLevytskyyVyacheslavLevytskyy
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[SPIR-V] Introduce support of '__spirv_' wrapper builtins for the SPV_INTEL_subgroups extension (#94235)
This PR Introduces support of '__spirv_' wrapper builtins for the SPV_INTEL_subgroups extension.
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‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

Lines changed: 9 additions & 1 deletion
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@@ -1020,9 +1020,17 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
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}
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const SPIRV::IntelSubgroupsBuiltin *IntelSubgroups =
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SPIRV::lookupIntelSubgroupsBuiltin(Builtin->Name);
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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uint32_t OpCode = IntelSubgroups->Opcode;
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if (Call->isSpirvOp()) {
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bool IsSet = OpCode != SPIRV::OpSubgroupBlockWriteINTEL &&
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OpCode != SPIRV::OpSubgroupImageBlockWriteINTEL;
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return buildOpFromWrapper(MIRBuilder, OpCode, Call,
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IsSet ? GR->getSPIRVTypeID(Call->ReturnType)
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: Register(0));
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}
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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if (IntelSubgroups->IsBlock) {
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// Minimal number or arguments set in TableGen records is 1
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if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) {

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td

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@@ -1055,6 +1055,21 @@ foreach i = ["", "2", "4", "8", "16"] in {
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}
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// OpSubgroupImageBlockReadINTEL and OpSubgroupImageBlockWriteINTEL are to be resolved later on (in code)
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// Multiclass used to define builtin wrappers for the SPV_INTEL_subgroups extension.
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multiclass DemangledIntelSubgroupsBuiltinWrapper<string name, bits<8> numArgs, Op operation> {
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def : DemangledBuiltin<!strconcat("__spirv_", name), OpenCL_std, IntelSubgroups, numArgs, numArgs>;
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def : IntelSubgroupsBuiltin<!strconcat("__spirv_", name), operation>;
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}
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleINTEL", 2, OpSubgroupShuffleINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleDownINTEL", 3, OpSubgroupShuffleDownINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleUpINTEL", 3, OpSubgroupShuffleUpINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleXorINTEL", 2, OpSubgroupShuffleXorINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupBlockReadINTEL", 1, OpSubgroupBlockReadINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupBlockWriteINTEL", 2, OpSubgroupBlockWriteINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupImageBlockReadINTEL", 2, OpSubgroupImageBlockReadINTEL>;
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defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupImageBlockWriteINTEL", 3, OpSubgroupImageBlockWriteINTEL>;
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//===----------------------------------------------------------------------===//
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// Class defining a builtin for group operations within uniform control flow.
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// It should be translated into a SPIR-V instruction using

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll

Lines changed: 84 additions & 0 deletions
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@@ -0,0 +1,84 @@
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; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s
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; CHECK-DAG: Capability SubgroupShuffleINTEL
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; CHECK-DAG: Capability SubgroupBufferBlockIOINTEL
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; CHECK-DAG: Capability SubgroupImageBlockIOINTEL
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; CHECK: Extension "SPV_INTEL_subgroups"
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; CHECK-DAG: %[[#Float:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#FloatVec:]] = OpTypeVector %[[#Float]] 2
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; CHECK-DAG: %[[#Int:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#IntVec:]] = OpTypeVector %[[#Int]] 2
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; CHECK: Function
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; CHECK: %[[#X:]] = OpFunctionParameter
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; CHECK: %[[#C:]] = OpFunctionParameter
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; CHECK: %[[#ImgIn:]] = OpFunctionParameter
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; CHECK: %[[#ImgOut:]] = OpFunctionParameter
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; CHECK: %[[#Coord:]] = OpFunctionParameter
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; CHECK: %[[#Ptr:]] = OpFunctionParameter
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; CHECK: %[[#]] = OpSubgroupShuffleINTEL %[[#FloatVec]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleDownINTEL %[[#FloatVec]] %[[#X]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleUpINTEL %[[#FloatVec]] %[[#X]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleXorINTEL %[[#FloatVec]] %[[#X]] %[[#C]]
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; CHECK: %[[#ResImg1:]] = OpSubgroupImageBlockReadINTEL %[[#IntVec]] %[[#ImgIn]] %[[#Coord]]
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; CHECK: OpSubgroupImageBlockWriteINTEL %[[#ImgOut]] %[[#Coord]] %[[#ResImg1]]
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; CHECK: %[[#Res1:]] = OpSubgroupBlockReadINTEL %[[#IntVec]] %[[#Ptr]]
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; CHECK: OpSubgroupBlockWriteINTEL %[[#Ptr]] %[[#Res1]]
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; CHECK: %[[#]] = OpSubgroupShuffleINTEL %[[#FloatVec]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleDownINTEL %[[#FloatVec]] %[[#X]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleUpINTEL %[[#FloatVec]] %[[#X]] %[[#X]] %[[#C]]
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; CHECK: %[[#]] = OpSubgroupShuffleXorINTEL %[[#FloatVec]] %[[#X]] %[[#C]]
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; CHECK: %[[#ResImg2:]] = OpSubgroupImageBlockReadINTEL %[[#IntVec]] %[[#ImgIn]] %[[#Coord]]
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; CHECK: OpSubgroupImageBlockWriteINTEL %[[#ImgOut]] %[[#Coord]] %[[#ResImg2]]
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; CHECK: %[[#Res2:]] = OpSubgroupBlockReadINTEL %[[#IntVec]] %[[#Ptr]]
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; CHECK: OpSubgroupBlockWriteINTEL %[[#Ptr]] %[[#Res2]]
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; CHECK: Return
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define spir_kernel void @test(<2 x float> %x, i32 %c, ptr addrspace(1) %image_in, ptr addrspace(1) %image_out, <2 x i32> %coord, ptr addrspace(1) %p) {
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entry:
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%wrap = tail call spir_func <2 x float> @__spirv_SubgroupShuffleINTEL(<2 x float> %x, i32 %c)
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%wrap1 = tail call spir_func <2 x float> @__spirv_SubgroupShuffleDownINTEL(<2 x float> %x, <2 x float> %x, i32 %c)
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%wrap2 = tail call spir_func <2 x float> @__spirv_SubgroupShuffleUpINTEL(<2 x float> %x, <2 x float> %x, i32 %c)
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%wrap3 = tail call spir_func <2 x float> @__spirv_SubgroupShuffleXorINTEL(<2 x float> %x, i32 %c)
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%wrap4 = tail call spir_func <2 x i32> @__spirv_SubgroupImageBlockReadINTEL(ptr addrspace(1) %image_in, <2 x i32> %coord)
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tail call spir_func void @__spirv_SubgroupImageBlockWriteINTEL(ptr addrspace(1) %image_out, <2 x i32> %coord, <2 x i32> %wrap4)
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%wrap5 = tail call spir_func <2 x i32> @__spirv_SubgroupBlockReadINTEL(ptr addrspace(1) %p)
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tail call spir_func void @__spirv_SubgroupBlockWriteINTEL(ptr addrspace(1) %p, <2 x i32> %wrap5)
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%ocl = tail call spir_func <2 x float> @intel_sub_group_shuffle(<2 x float> %x, i32 %c)
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%ocl1 = tail call spir_func <2 x float> @intel_sub_group_shuffle_down(<2 x float> %x, <2 x float> %x, i32 %c)
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%ocl2 = tail call spir_func <2 x float> @intel_sub_group_shuffle_up(<2 x float> %x, <2 x float> %x, i32 %c)
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%ocl3 = tail call spir_func <2 x float> @intel_sub_group_shuffle_xor(<2 x float> %x, i32 %c)
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%ocl4 = tail call spir_func <2 x i32> @_Z27intel_sub_group_block_read214ocl_image2d_roDv2_i(ptr addrspace(1) %image_in, <2 x i32> %coord)
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tail call spir_func void @_Z28intel_sub_group_block_write214ocl_image2d_woDv2_iDv2_j(ptr addrspace(1) %image_out, <2 x i32> %coord, <2 x i32> %ocl4)
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%ocl5 = tail call spir_func <2 x i32> @intel_sub_group_block_read(ptr addrspace(1) %p)
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tail call spir_func void @intel_sub_group_block_write(ptr addrspace(1) %p, <2 x i32> %ocl5)
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ret void
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}
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declare spir_func <2 x float> @__spirv_SubgroupShuffleINTEL(<2 x float>, i32)
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declare spir_func <2 x float> @__spirv_SubgroupShuffleDownINTEL(<2 x float>, <2 x float>, i32)
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declare spir_func <2 x float> @__spirv_SubgroupShuffleUpINTEL(<2 x float>, <2 x float>, i32)
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declare spir_func <2 x float> @__spirv_SubgroupShuffleXorINTEL(<2 x float>, i32)
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declare spir_func <2 x i32> @__spirv_SubgroupBlockReadINTEL(ptr addrspace(1))
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declare spir_func void @__spirv_SubgroupBlockWriteINTEL(ptr addrspace(1), <2 x i32>)
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declare spir_func <2 x i32> @__spirv_SubgroupImageBlockReadINTEL(ptr addrspace(1), <2 x i32>)
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declare spir_func void @__spirv_SubgroupImageBlockWriteINTEL(ptr addrspace(1), <2 x i32>, <2 x i32>)
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declare spir_func <2 x float> @intel_sub_group_shuffle(<2 x float>, i32)
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declare spir_func <2 x float> @intel_sub_group_shuffle_down(<2 x float>, <2 x float>, i32)
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declare spir_func <2 x float> @intel_sub_group_shuffle_up(<2 x float>, <2 x float>, i32)
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declare spir_func <2 x float> @intel_sub_group_shuffle_xor(<2 x float>, i32)
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declare spir_func <2 x i32> @intel_sub_group_block_read(ptr addrspace(1))
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declare spir_func void @intel_sub_group_block_write(ptr addrspace(1), <2 x i32>)
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declare spir_func <2 x i32> @_Z27intel_sub_group_block_read214ocl_image2d_roDv2_i(ptr addrspace(1), <2 x i32>)
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declare spir_func void @_Z28intel_sub_group_block_write214ocl_image2d_woDv2_iDv2_j(ptr addrspace(1), <2 x i32>, <2 x i32>)

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