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[DAGCombiner][AArch64] Prevent SimplifyVCastOp from creating illegal scalar types after type legalization. (#148970)
Fixes #148949
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2 files changed

+32
-8
lines changed

2 files changed

+32
-8
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28187,14 +28187,16 @@ SDValue DAGCombiner::SimplifyVCastOp(SDNode *N, const SDLoc &DL) {
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TLI.preferScalarizeSplat(N)) {
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EVT SrcVT = N0.getValueType();
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EVT SrcEltVT = SrcVT.getVectorElementType();
28190-
SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL);
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SDValue Elt =
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcEltVT, Src0, IndexC);
28193-
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags());
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if (VT.isScalableVector())
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return DAG.getSplatVector(VT, DL, ScalarBO);
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SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
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return DAG.getBuildVector(VT, DL, Ops);
28190+
if (!LegalTypes || TLI.isTypeLegal(SrcEltVT)) {
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SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL);
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SDValue Elt =
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcEltVT, Src0, IndexC);
28194+
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags());
28195+
if (VT.isScalableVector())
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return DAG.getSplatVector(VT, DL, ScalarBO);
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SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
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return DAG.getBuildVector(VT, DL, Ops);
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}
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}
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return SDValue();

llvm/test/CodeGen/AArch64/pr148949.ll

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s
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define <vscale x 4 x i8> @widget(i1 %arg, <vscale x 4 x i1> %arg1, <vscale x 4 x i8> %arg2, <vscale x 4 x i8> %arg3) {
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; CHECK-LABEL: widget:
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; CHECK: // %bb.0: // %bb
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: sbfx x8, x8, #0, #1
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; CHECK-NEXT: whilelo p1.s, xzr, x8
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; CHECK-NEXT: mov z1.s, p1/z, #1 // =0x1
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; CHECK-NEXT: orr z0.d, z1.d, z0.d
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; CHECK-NEXT: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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bb:
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%insertelement = insertelement <vscale x 4 x i1> zeroinitializer, i1 %arg, i64 0
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%shufflevector = shufflevector <vscale x 4 x i1> %insertelement, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> zeroinitializer
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%xor = xor <vscale x 4 x i1> %shufflevector, splat (i1 true)
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%zext = zext <vscale x 4 x i1> %xor to <vscale x 4 x i8>
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%select = select <vscale x 4 x i1> %arg1, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %arg2
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%or = or <vscale x 4 x i8> %select, %zext
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ret <vscale x 4 x i8> %or
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}

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