@@ -16785,7 +16785,7 @@ static void knownBitsForWorkitemID(const GCNSubtarget &ST,
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static void knownBitsForSBFE(const MachineInstr &MI, GISelValueTracking &VT,
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KnownBits &Known, const APInt &DemandedElts,
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- unsigned BFEWidth, bool SExt) {
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+ unsigned BFEWidth, bool SExt, unsigned Depth ) {
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const MachineRegisterInfo &MRI = VT.getMachineFunction().getRegInfo();
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const MachineOperand &Src1 = MI.getOperand(2);
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@@ -16807,7 +16807,8 @@ static void knownBitsForSBFE(const MachineInstr &MI, GISelValueTracking &VT,
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Src1Cst & maskTrailingOnes<unsigned>((BFEWidth == 32) ? 5 : 6);
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const unsigned Width = (Src1Cst >> 16) & maskTrailingOnes<unsigned>(6);
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- VT.computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts);
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+ VT.computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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+ Depth + 1);
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Known.Zero = Known.Zero.lshr(Offset);
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Known.One = Known.One.lshr(Offset);
@@ -16829,16 +16830,16 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
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switch (MI->getOpcode()) {
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case AMDGPU::S_BFE_I32:
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return knownBitsForSBFE(*MI, VT, Known, DemandedElts, /*Width=*/32,
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- /*SExt=*/true);
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+ /*SExt=*/true, Depth );
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case AMDGPU::S_BFE_U32:
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return knownBitsForSBFE(*MI, VT, Known, DemandedElts, /*Width=*/32,
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- /*SExt=*/false);
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+ /*SExt=*/false, Depth );
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case AMDGPU::S_BFE_I64:
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return knownBitsForSBFE(*MI, VT, Known, DemandedElts, /*Width=*/64,
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- /*SExt=*/true);
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+ /*SExt=*/true, Depth );
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case AMDGPU::S_BFE_U64:
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return knownBitsForSBFE(*MI, VT, Known, DemandedElts, /*Width=*/64,
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- /*SExt=*/false);
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+ /*SExt=*/false, Depth );
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case AMDGPU::G_INTRINSIC:
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case AMDGPU::G_INTRINSIC_CONVERGENT: {
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Intrinsic::ID IID = cast<GIntrinsic>(MI)->getIntrinsicID();
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