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[TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (#136655)
These are not diagnosed because implementations hide the methods of the base class rather than overriding them. This works as long as a hiding function is callable with the same arguments as the same function from the base class. Pull Request: #136655
1 parent ef72b93 commit 3334c35

26 files changed

+84
-91
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3101,10 +3101,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
31013101
return Impl.areTypesABICompatible(Caller, Callee, Types);
31023102
}
31033103
bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override {
3104-
return Impl.isIndexedLoadLegal(Mode, Ty, getDataLayout());
3104+
return Impl.isIndexedLoadLegal(Mode, Ty);
31053105
}
31063106
bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override {
3107-
return Impl.isIndexedStoreLegal(Mode, Ty, getDataLayout());
3107+
return Impl.isIndexedStoreLegal(Mode, Ty);
31083108
}
31093109
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override {
31103110
return Impl.getLoadStoreVecRegBitWidth(AddrSpace);

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -471,7 +471,9 @@ class TargetTransformInfoImplBase {
471471

472472
bool haveFastSqrt(Type *Ty) const { return false; }
473473

474-
bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
474+
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const {
475+
return true;
476+
}
475477

476478
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
477479

@@ -745,9 +747,10 @@ class TargetTransformInfoImplBase {
745747
return 1;
746748
}
747749

748-
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
749-
const APInt &DemandedDstElts,
750-
TTI::TargetCostKind CostKind) const {
750+
InstructionCost
751+
getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
752+
const APInt &DemandedDstElts,
753+
TTI::TargetCostKind CostKind) const {
751754
return 1;
752755
}
753756

@@ -805,7 +808,7 @@ class TargetTransformInfoImplBase {
805808
return InstructionCost::getInvalid();
806809
}
807810

808-
unsigned getInterleavedMemoryOpCost(
811+
InstructionCost getInterleavedMemoryOpCost(
809812
unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
810813
Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
811814
bool UseMaskForCond, bool UseMaskForGaps) const {
@@ -965,13 +968,11 @@ class TargetTransformInfoImplBase {
965968
Callee->getFnAttribute("target-features"));
966969
}
967970

968-
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty,
969-
const DataLayout &DL) const {
971+
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const {
970972
return false;
971973
}
972974

973-
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty,
974-
const DataLayout &DL) const {
975+
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const {
975976
return false;
976977
}
977978

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -475,19 +475,17 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
475475
return VF;
476476
}
477477

478-
bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty,
479-
const DataLayout &DL) const {
478+
bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty) const {
480479
EVT VT = getTLI()->getValueType(DL, Ty);
481480
return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT);
482481
}
483482

484-
bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty,
485-
const DataLayout &DL) const {
483+
bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty) const {
486484
EVT VT = getTLI()->getValueType(DL, Ty);
487485
return getTLI()->isIndexedStoreLegal(getISDIndexedMode(M), VT);
488486
}
489487

490-
bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) const {
488+
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
491489
return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
492490
}
493491

@@ -1468,7 +1466,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
14681466
}
14691467

14701468
InstructionCost getMemoryOpCost(
1471-
unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace,
1469+
unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
14721470
TTI::TargetCostKind CostKind,
14731471
TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
14741472
const Instruction *I = nullptr) const {

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4367,7 +4367,7 @@ bool AArch64TTIImpl::useNeonVector(const Type *Ty) const {
43674367
}
43684368

43694369
InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
4370-
MaybeAlign Alignment,
4370+
Align Alignment,
43714371
unsigned AddressSpace,
43724372
TTI::TargetCostKind CostKind,
43734373
TTI::OperandValueInfo OpInfo,
@@ -4402,7 +4402,7 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
44024402
return 1;
44034403

44044404
if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
4405-
LT.second.is128BitVector() && (!Alignment || *Alignment < Align(16))) {
4405+
LT.second.is128BitVector() && Alignment < Align(16)) {
44064406
// Unaligned stores are extremely inefficient. We don't split all
44074407
// unaligned 128-bit stores because the negative impact that has shown in
44084408
// practice on inlined block copy code.
@@ -4429,8 +4429,7 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
44294429
EVT EltVT = VT.getVectorElementType();
44304430
unsigned EltSize = EltVT.getScalarSizeInBits();
44314431
if (!isPowerOf2_32(EltSize) || EltSize < 8 || EltSize > 64 ||
4432-
VT.getVectorNumElements() >= (128 / EltSize) || !Alignment ||
4433-
*Alignment != Align(1))
4432+
VT.getVectorNumElements() >= (128 / EltSize) || Alignment != Align(1))
44344433
return LT.first;
44354434
// FIXME: v3i8 lowering currently is very inefficient, due to automatic
44364435
// widening to v4i8, which produces suboptimal results.

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
249249
bool useNeonVector(const Type *Ty) const;
250250

251251
InstructionCost getMemoryOpCost(
252-
unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace,
252+
unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
253253
TTI::TargetCostKind CostKind,
254254
TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
255255
const Instruction *I = nullptr) const;

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,7 @@ void AMDGPUTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
274274
BaseT::getPeelingPreferences(L, SE, PP);
275275
}
276276

277-
int64_t AMDGPUTTIImpl::getMaxMemIntrinsicInlineSizeThreshold() const {
277+
uint64_t AMDGPUTTIImpl::getMaxMemIntrinsicInlineSizeThreshold() const {
278278
return 1024;
279279
}
280280

@@ -412,7 +412,7 @@ bool GCNTTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
412412
return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
413413
}
414414

415-
int64_t GCNTTIImpl::getMaxMemIntrinsicInlineSizeThreshold() const {
415+
uint64_t GCNTTIImpl::getMaxMemIntrinsicInlineSizeThreshold() const {
416416
return 1024;
417417
}
418418

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
5757
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
5858
TTI::PeelingPreferences &PP) const;
5959

60-
int64_t getMaxMemIntrinsicInlineSizeThreshold() const;
60+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
6161
};
6262

6363
class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
@@ -137,7 +137,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
137137
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
138138
unsigned AddrSpace) const;
139139

140-
int64_t getMaxMemIntrinsicInlineSizeThreshold() const;
140+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
141141
Type *
142142
getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
143143
unsigned SrcAddrSpace, unsigned DestAddrSpace,

‎llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ unsigned R600TTIImpl::getHardwareNumberOfRegisters(bool Vec) const {
3232
return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
3333
}
3434

35-
unsigned R600TTIImpl::getNumberOfRegisters(bool Vec) const {
35+
unsigned R600TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
36+
bool Vec = ClassID == 1;
3637
return getHardwareNumberOfRegisters(Vec);
3738
}
3839

‎llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
4747
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
4848
TTI::PeelingPreferences &PP) const;
4949
unsigned getHardwareNumberOfRegisters(bool Vec) const;
50-
unsigned getNumberOfRegisters(bool Vec) const;
50+
unsigned getNumberOfRegisters(unsigned ClassID) const;
5151
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
5252
unsigned getMinVectorRegisterBitWidth() const;
5353
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1545,7 +1545,7 @@ InstructionCost ARMTTIImpl::getArithmeticInstrCost(
15451545
}
15461546

15471547
InstructionCost ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
1548-
MaybeAlign Alignment,
1548+
Align Alignment,
15491549
unsigned AddressSpace,
15501550
TTI::TargetCostKind CostKind,
15511551
TTI::OperandValueInfo OpInfo,
@@ -1559,8 +1559,7 @@ InstructionCost ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
15591559
return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
15601560
CostKind);
15611561

1562-
if (ST->hasNEON() && Src->isVectorTy() &&
1563-
(Alignment && *Alignment != Align(16)) &&
1562+
if (ST->hasNEON() && Src->isVectorTy() && Alignment != Align(16) &&
15641563
cast<VectorType>(Src)->getElementType()->isDoubleTy()) {
15651564
// Unaligned loads/stores are extremely inefficient.
15661565
// We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.

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