[PowerPC] Support for Packed BCD conversion builtins (#142723)

Support the following packed BCD builtins for PowerPC.
  
```
__builtin_national2packed - Conversion of National format to Packed decimal format.
__builtin_packed2national - Conversion of Packed decimal format to national format.
__builtin_packed2zoned    - Conversion of Packed decimal format to Zoned decimal format.
__builtin_zoned2packed    - Conversion of Zoned decimal format to Packed decimal format.
```
### Prototypes: 
`vector unsigned char __builtin_national2packed(vector unsigned char a,
unsigned char b);`
`vector unsigned char __builtin_packed2zoned(vector unsigned char,
unsigned char);`
`vector unsigned char __builtin_zoned2packed(vector unsigned char,
unsigned char);`

The condition for the 2nd parameter is consistent over all the 3
prototypes (0 or 1 only).

`vector unsigned char __builtin_packed2national(vector unsigned char);`

Co-authored-by: himadhith <himadhith.v@ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil@gmail.com>

Author: 3 people

clang/include/clang/Basic/BuiltinsPPC.def

@@ -535,6 +535,12 @@ TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "",
 TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "",
                "isa-v207-instructions")
 
+// P9 Binary-coded decimal (BCD) builtins.                                                
+TARGET_BUILTIN(__builtin_ppc_national2packed, "V16UcV16UcUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_packed2national, "V16UcV16Uc", "", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_packed2zoned, "V16UcV16UcUc", "t", "power9-vector")
+TARGET_BUILTIN(__builtin_ppc_zoned2packed, "V16UcV16UcUc", "t", "power9-vector")
+
 TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector")

clang/lib/Basic/Targets/PPC.cpp

@@ -89,6 +89,12 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
 }
 
 static void defineXLCompatMacros(MacroBuilder &Builder) {
+  Builder.defineMacro("__builtin_national2packed",
+                      "__builtin_ppc_national2packed");
+  Builder.defineMacro("__builtin_packed2national",
+                      "__builtin_ppc_packed2national");
+  Builder.defineMacro("__builtin_packed2zoned", "__builtin_ppc_packed2zoned");
+  Builder.defineMacro("__builtin_zoned2packed", "__builtin_ppc_zoned2packed");
   Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
   Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
   Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");

clang/lib/Sema/SemaPPC.cpp

@@ -106,6 +106,10 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI,
   switch (BuiltinID) {
   default:
     return false;
+  case PPC::BI__builtin_ppc_national2packed:
+  case PPC::BI__builtin_ppc_packed2zoned:
+  case PPC::BI__builtin_ppc_zoned2packed:
+    return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_altivec_crypto_vshasigmaw:
   case PPC::BI__builtin_altivec_crypto_vshasigmad:
     return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) ||

clang/test/CodeGen/PowerPC/builtins-bcd-transform.c

@@ -0,0 +1,79 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// Testfile that verifies positive cases (0 or 1 only) for BCD builtins national2packed, packed2zoned and zoned2packed.
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_National2packed_imm1(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.national2packed(<16 x i8> [[A]], i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_National2packed_imm1(vector unsigned char a) {
+    return __builtin_ppc_national2packed (a,'\1');
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_National2packed_imm0(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.national2packed(<16 x i8> [[A]], i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_National2packed_imm0(vector unsigned char a) {
+    return __builtin_ppc_national2packed (a,'\0');
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_Packed2national(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.packed2national(<16 x i8> [[A]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_Packed2national(vector unsigned char a){
+    return __builtin_ppc_packed2national(a);
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_Packed2zoned_imm0(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.packed2zoned(<16 x i8> [[A]], i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_Packed2zoned_imm0(vector unsigned char a){
+    return __builtin_ppc_packed2zoned(a,'\0');
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_Packed2zoned_imm1(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.packed2zoned(<16 x i8> [[A]], i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_Packed2zoned_imm1(vector unsigned char a){
+    return __builtin_ppc_packed2zoned(a,'\1');
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_Zoned2packed_imm0(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.zoned2packed(<16 x i8> [[A]], i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_Zoned2packed_imm0(vector unsigned char a){
+    return __builtin_ppc_zoned2packed(a,'\0');
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @tBcd_Zoned2packed_imm1(
+// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.zoned2packed(<16 x i8> [[A]], i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+vector unsigned char tBcd_Zoned2packed_imm1(vector unsigned char a){
+    return __builtin_ppc_zoned2packed(a,'\1');
+}

clang/test/Sema/builtins-bcd-transform.c

@@ -0,0 +1,30 @@
+// Testfile to verify the semantics and the error handling for BCD builtins national2packed, packed2zoned and zoned2packed.
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown -fsyntax-only -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -fsyntax-only -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -fsyntax-only -verify %s
+
+#include <altivec.h>
+vector unsigned char test_national2packed(void)
+{
+  vector unsigned char a = {1,2,3,4};
+  vector unsigned char res_a = __builtin_ppc_national2packed(a, 2);  // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  vector unsigned char res_b = __builtin_ppc_national2packed(a, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  return __builtin_ppc_national2packed(a, 0);
+}
+
+vector unsigned char test_packed2zoned(void)
+{
+  vector unsigned char a = {1,2,3,4};
+  vector unsigned char res_a = __builtin_ppc_packed2zoned(a,2);  // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  vector unsigned char res_b = __builtin_ppc_packed2zoned(a, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  return __builtin_ppc_packed2zoned(a,1);
+}
+
+vector unsigned char test_zoned2packed(void)
+{
+  vector unsigned char a = {1,2,3,4};
+  vector unsigned char res_a = __builtin_ppc_zoned2packed(a,2);  // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  vector unsigned char res_b = __builtin_ppc_zoned2packed(a, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  return __builtin_ppc_zoned2packed(a,0);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

@@ -655,6 +655,14 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
       DefaultAttrsIntrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
 
   // BCD intrinsics.
+  def int_ppc_national2packed: ClangBuiltin<"__builtin_ppc_national2packed">,
+    DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_ppc_packed2national: ClangBuiltin<"__builtin_ppc_packed2national">,
+    DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_packed2zoned: ClangBuiltin<"__builtin_ppc_packed2zoned">,
+    DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_ppc_zoned2packed: ClangBuiltin<"__builtin_ppc_zoned2packed">,
+    DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
   def int_ppc_cdtbcdd : ClangBuiltin<"__builtin_ppc_cdtbcd">,
     DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_cbcdtdd: ClangBuiltin<"__builtin_ppc_cbcdtd">,

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

@@ -1617,10 +1617,14 @@ class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
 }
 
 // Decimal Convert From/to National/Zoned/Signed-QWord
-def BCDCFN_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
-def BCDCFZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
-def BCDCTN_rec  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
-def BCDCTZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
+def BCDCFN_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." ,
+                  [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, timm:$PS))]>;
+def BCDCFZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , 
+                  [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, timm:$PS))]>;
+def BCDCTN_rec  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , 
+                  [(set v16i8:$VD, (int_ppc_packed2national v16i8:$VB))]>;
+def BCDCTZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , 
+                  [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, timm:$PS))]>;
 def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
 def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
 

llvm/test/CodeGen/PowerPC/builtins-bcd-transform.ll

@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Testfile that verifies positive case (0 or 1 only) for BCD builtins national2packed, packed2zoned and zoned2packed.
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names  < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names  < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names  < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:   -ppc-asm-full-reg-names  < %s | FileCheck %s
+
+declare <16 x i8> @llvm.ppc.national2packed(<16 x i8>, i32 immarg)
+
+define <16 x i8> @tBcd_National2packed_imm0(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_National2packed_imm0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdcfn. v2, v2, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.national2packed(<16 x i8> %a, i32 0)
+  ret <16 x i8> %0
+}
+
+define <16 x i8> @tBcd_National2packed_imm1(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_National2packed_imm1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdcfn. v2, v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.national2packed(<16 x i8> %a, i32 1)
+  ret <16 x i8> %0
+}
+
+declare <16 x i8> @llvm.ppc.packed2national(<16 x i8>)
+
+define <16 x i8> @tBcd_Packed2national(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_Packed2national:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdctn. v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.packed2national(<16 x i8> %a)
+  ret <16 x i8> %0
+}
+
+declare <16 x i8> @llvm.ppc.packed2zoned(<16 x i8>, i32 immarg)
+
+define <16 x i8> @tBcd_Packed2zoned_imm0(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_Packed2zoned_imm0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdctz. v2, v2, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.packed2zoned(<16 x i8> %a, i32 0)
+  ret <16 x i8> %0
+}
+
+define <16 x i8> @tBcd_Packed2zoned_imm1(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_Packed2zoned_imm1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdctz. v2, v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.packed2zoned(<16 x i8> %a, i32 1)
+  ret <16 x i8> %0
+}
+
+declare <16 x i8> @llvm.ppc.zoned2packed(<16 x i8>, i32 immarg)
+
+define <16 x i8> @tBcd_Zoned2packed_imm0(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_Zoned2packed_imm0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdcfz. v2, v2, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.zoned2packed(<16 x i8> %a, i32 0)
+  ret <16 x i8> %0
+}
+
+define <16 x i8> @tBcd_Zoned2packed_imm1(<16 x i8> %a) {
+; CHECK-LABEL: tBcd_Zoned2packed_imm1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bcdcfz. v2, v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = call <16 x i8> @llvm.ppc.zoned2packed(<16 x i8> %a, i32 1)
+  ret <16 x i8> %0
+}