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llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4839,23 +4839,26 @@ static bool isFloatingPointZero(SDValue Op) {
48394839
return false;
48404840
}
48414841

4842-
// TODO: This is copied from AArch64TargetLowering.cpp, which only has
4843-
// ands, subs, and adds affecting flags. In ARM, we have more than that, so this
4844-
// should be expanded to cover all the cases where we can adjust the condition
4845-
// code to zero.
48464842
static bool shouldBeAdjustedToZero(SDValue LHS, APInt C, ISD::CondCode &CC) {
4847-
// Special case where we can use pl or mi instead of lt or ge.
4848-
// Any instruction that sets flags can be optimized to use mi or pl
4849-
// this way.
4843+
// TODO: Can we know ahead of time if we can use a MOVS?
4844+
switch (LHS.getOpcode()) {
4845+
case ISD::AND:
4846+
case ISD::OR:
4847+
case ISD::XOR:
4848+
case ISD::ADD:
4849+
case ISD::SUB:
4850+
case ISD::MUL:
4851+
// In ARM, almost every instruction has a variant that sets flags.
4852+
break;
4853+
default:
4854+
return false;
4855+
}
4856+
48504857
if (C.isAllOnes() && (CC == ISD::SETLE || CC == ISD::SETGT)) {
48514858
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
48524859
return true;
48534860
}
48544861

4855-
// TODO: Cover all cases where a comparison with 0 would be profitable...
4856-
if (LHS.getOpcode() != ISD::AND)
4857-
return false;
4858-
48594862
if (C.isOne() && (CC == ISD::SETLT || CC == ISD::SETGE)) {
48604863
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
48614864
return true;

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