[Hexagon]Handle truncate of v4i8/v2i16 -> v4i1/v2i1 when Hvx is enabled

Change-Id: Id1c25dfbaf95a56b687eb6e47d2e48c8fe84deaf

Author: pkarveti

llvm/lib/Target/Hexagon/HexagonPatterns.td

@@ -582,6 +582,13 @@ def: Pat<(v8i1 (trunc V8I8:$Rs)),
          (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)),
                                 (A2_andir (LoReg $Rs), (i32 0x01010101))),
                       (i32 1))>;
+def : Pat<(v4i1 (trunc V4I8:$Rs)),
+          (A4_vcmpheqi (Combinew (A2_andir (HiReg (S2_vzxtbh $Rs)), 0x00010001),
+                                 (A2_andir (LoReg (S2_vzxtbh $Rs)), 0x00010001)),
+                       (i32 1))>;
+def: Pat<(v2i1 (trunc V2I16:$Rs)),
+          (A4_vcmpweqi (A2_andp (S2_vzxthw $Rs), (A2_combineii (i32 1), (i32 1))),
+                      (i32 1))>;
 
 
 // Saturation:

llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll

@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
 
 define void @f0(<2 x i32> %a0, ptr %a1) {
 ; CHECK-LABEL: f0:
@@ -68,3 +69,53 @@ b0:
   store <8 x i1> %v0, ptr %a1, align 1
   ret void
 }
+
+define void @f3(<4 x i8> %a0, ptr %a1) {
+; CHECK-LABEL: f3:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3:2 = vzxtbh(r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = and(r2,##65537)
+; CHECK-NEXT:     r3 = and(r3,##65537)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = vcmph.eq(r3:2,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r1+#0) = r2.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = trunc <4 x i8> %a0 to <4 x i1>
+  store <4 x i1> %v0, ptr %a1, align 1
+  ret void
+}
+
+define void @f4(<2 x i16> %a0, ptr %a1) {
+; CHECK-LABEL: f4:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3:2 = vzxthw(r0)
+; CHECK-NEXT:     r5:4 = combine(#1,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3:2 = and(r3:2,r5:4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = vcmpw.eq(r3:2,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r1+#0) = r2.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = trunc <2 x i16> %a0 to <2 x i1>
+  store <2 x i1> %v0, ptr %a1, align 1
+  ret void
+}