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[NFC][TableGen] Cleanup iterators in CodeGenSchedule.h (#127401)
- Use range for loops for processor models and schedule classes. - Cleanup duplicated or unused iterators in CodeGenSchedule.h
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3 files changed

+42
-79
lines changed

3 files changed

+42
-79
lines changed

llvm/utils/TableGen/Common/CodeGenSchedule.h

Lines changed: 5 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -467,23 +467,6 @@ class CodeGenSchedModels {
467467
public:
468468
CodeGenSchedModels(const RecordKeeper &RK, const CodeGenTarget &TGT);
469469

470-
// iterator access to the scheduling classes.
471-
using class_iterator = std::vector<CodeGenSchedClass>::iterator;
472-
using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
473-
class_iterator classes_begin() { return SchedClasses.begin(); }
474-
const_class_iterator classes_begin() const { return SchedClasses.begin(); }
475-
class_iterator classes_end() { return SchedClasses.end(); }
476-
const_class_iterator classes_end() const { return SchedClasses.end(); }
477-
iterator_range<class_iterator> classes() {
478-
return make_range(classes_begin(), classes_end());
479-
}
480-
iterator_range<const_class_iterator> classes() const {
481-
return make_range(classes_begin(), classes_end());
482-
}
483-
ArrayRef<CodeGenSchedClass> explicit_classes() const {
484-
return ArrayRef(SchedClasses).take_front(NumInstrSchedClasses);
485-
}
486-
487470
const Record *getModelOrItinDef(const Record *ProcDef) const {
488471
const Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
489472
const Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
@@ -497,13 +480,13 @@ class CodeGenSchedModels {
497480

498481
const CodeGenProcModel &getModelForProc(const Record *ProcDef) const {
499482
const Record *ModelDef = getModelOrItinDef(ProcDef);
500-
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
483+
auto I = ProcModelMap.find(ModelDef);
501484
assert(I != ProcModelMap.end() && "missing machine model");
502485
return ProcModels[I->second];
503486
}
504487

505488
const CodeGenProcModel &getProcModel(const Record *ModelDef) const {
506-
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
489+
auto I = ProcModelMap.find(ModelDef);
507490
assert(I != ProcModelMap.end() && "missing machine model");
508491
return ProcModels[I->second];
509492
}
@@ -512,10 +495,6 @@ class CodeGenSchedModels {
512495
static_cast<const CodeGenSchedModels &>(*this).getProcModel(ModelDef));
513496
}
514497

515-
// Iterate over the unique processor models.
516-
using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
517-
ProcIter procModelBegin() const { return ProcModels.begin(); }
518-
ProcIter procModelEnd() const { return ProcModels.end(); }
519498
ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
520499

521500
// Return true if any processors have itineraries.
@@ -564,10 +543,10 @@ class CodeGenSchedModels {
564543
// for NoItinerary.
565544
unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
566545

567-
using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
568-
SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
569-
SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
570546
ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
547+
ArrayRef<CodeGenSchedClass> explicitSchedClasses() const {
548+
return schedClasses().take_front(NumInstrSchedClasses);
549+
}
571550

572551
unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
573552

llvm/utils/TableGen/InstrInfoEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1244,7 +1244,7 @@ void InstrInfoEmitter::emitEnums(
12441244
OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
12451245
OS << "namespace llvm::" << Namespace << "::Sched {\n\n";
12461246
OS << " enum {\n";
1247-
auto ExplictClasses = SchedModels.explicit_classes();
1247+
auto ExplictClasses = SchedModels.explicitSchedClasses();
12481248
for (const auto &[Idx, Class] : enumerate(ExplictClasses))
12491249
OS << " " << Class.Name << "\t= " << Idx << ",\n";
12501250
OS << " SCHED_LIST_END = " << ExplictClasses.size() << '\n';

llvm/utils/TableGen/SubtargetEmitter.cpp

Lines changed: 36 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ class SubtargetEmitter {
106106
void emitStageAndOperandCycleData(
107107
raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
108108
void emitItineraries(raw_ostream &OS,
109-
std::vector<std::vector<InstrItinerary>> &ProcItinLists);
109+
ArrayRef<std::vector<InstrItinerary>> ProcItinLists);
110110
unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,
111111
raw_ostream &OS);
112112
void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
@@ -477,7 +477,6 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
477477

478478
// Emit functional units for all the itineraries.
479479
for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
480-
481480
if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
482481
continue;
483482

@@ -489,25 +488,23 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
489488
OS << "\n// Functional units for \"" << Name << "\"\n"
490489
<< "namespace " << Name << "FU {\n";
491490

492-
for (unsigned J = 0, FUN = FUs.size(); J < FUN; ++J)
493-
OS << " const InstrStage::FuncUnits " << FUs[J]->getName()
494-
<< " = 1ULL << " << J << ";\n";
491+
for (const auto &[Idx, FU] : enumerate(FUs))
492+
OS << " const InstrStage::FuncUnits " << FU->getName() << " = 1ULL << "
493+
<< Idx << ";\n";
495494

496495
OS << "} // end namespace " << Name << "FU\n";
497496

498497
ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
499-
if (!BPs.empty()) {
500-
OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
501-
<< "\"\n"
502-
<< "namespace " << Name << "Bypass {\n";
498+
if (BPs.empty())
499+
continue;
500+
OS << "\n// Pipeline forwarding paths for itineraries \"" << Name << "\"\n"
501+
<< "namespace " << Name << "Bypass {\n";
503502

504-
OS << " const unsigned NoBypass = 0;\n";
505-
for (unsigned J = 0, BPN = BPs.size(); J < BPN; ++J)
506-
OS << " const unsigned " << BPs[J]->getName() << " = 1 << " << J
507-
<< ";\n";
503+
OS << " const unsigned NoBypass = 0;\n";
504+
for (const auto &[Idx, BP] : enumerate(BPs))
505+
OS << " const unsigned " << BP->getName() << " = 1 << " << Idx << ";\n";
508506

509-
OS << "} // end namespace " << Name << "Bypass\n";
510-
}
507+
OS << "} // end namespace " << Name << "Bypass\n";
511508
}
512509

513510
// Begin stages table
@@ -647,46 +644,39 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
647644
// CodeGenSchedClass::Index.
648645
//
649646
void SubtargetEmitter::emitItineraries(
650-
raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
647+
raw_ostream &OS, ArrayRef<std::vector<InstrItinerary>> ProcItinLists) {
651648
// Multiple processor models may share an itinerary record. Emit it once.
652649
SmallPtrSet<const Record *, 8> ItinsDefSet;
653650

654-
// For each processor's machine model
655-
std::vector<std::vector<InstrItinerary>>::iterator ProcItinListsIter =
656-
ProcItinLists.begin();
657-
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
658-
PE = SchedModels.procModelEnd();
659-
PI != PE; ++PI, ++ProcItinListsIter) {
660-
661-
const Record *ItinsDef = PI->ItinsDef;
651+
for (const auto &[Proc, ItinList] :
652+
zip_equal(SchedModels.procModels(), ProcItinLists)) {
653+
const Record *ItinsDef = Proc.ItinsDef;
662654
if (!ItinsDefSet.insert(ItinsDef).second)
663655
continue;
664656

665-
// Get the itinerary list for the processor.
666-
assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
667-
std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
668-
669657
// Empty itineraries aren't referenced anywhere in the tablegen output
670658
// so don't emit them.
671659
if (ItinList.empty())
672660
continue;
673661

662+
// Begin processor itinerary table
674663
OS << "\n";
675-
OS << "static const llvm::InstrItinerary ";
664+
OS << "static constexpr llvm::InstrItinerary " << ItinsDef->getName()
665+
<< "[] = {\n";
676666

677-
// Begin processor itinerary table
678-
OS << ItinsDef->getName() << "[] = {\n";
667+
ArrayRef<CodeGenSchedClass> ItinSchedClasses =
668+
SchedModels.schedClasses().take_front(ItinList.size());
679669

680670
// For each itinerary class in CodeGenSchedClass::Index order.
681-
for (unsigned J = 0, M = ItinList.size(); J < M; ++J) {
682-
InstrItinerary &Intinerary = ItinList[J];
683-
671+
for (const auto &[Idx, Intinerary, SchedClass] :
672+
enumerate(ItinList, ItinSchedClasses)) {
684673
// Emit Itinerary in the form of
685-
// { firstStage, lastStage, firstCycle, lastCycle } // index
674+
// { NumMicroOps, FirstStage, LastStage, FirstOperandCycle,
675+
// LastOperandCycle } // index class name
686676
OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage
687677
<< ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle
688-
<< ", " << Intinerary.LastOperandCycle << " }"
689-
<< ", // " << J << " " << SchedModels.getSchedClass(J).Name << "\n";
678+
<< ", " << Intinerary.LastOperandCycle << " }" << ", // " << Idx << " "
679+
<< SchedClass.Name << "\n";
690680
}
691681
// End processor itinerary table
692682
OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
@@ -1442,18 +1432,16 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
14421432
OS << "}; // " << Target << "ReadAdvanceTable\n";
14431433

14441434
// Emit a SchedClass table for each processor.
1445-
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1446-
PE = SchedModels.procModelEnd();
1447-
PI != PE; ++PI) {
1448-
if (!PI->hasInstrSchedModel())
1435+
for (const auto &[Idx, Proc] : enumerate(SchedModels.procModels())) {
1436+
if (!Proc.hasInstrSchedModel())
14491437
continue;
14501438

14511439
std::vector<MCSchedClassDesc> &SCTab =
1452-
SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
1440+
SchedTables.ProcSchedClasses[1 + Idx];
14531441

14541442
OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
14551443
<< " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1456-
OS << "static const llvm::MCSchedClassDesc " << PI->ModelName
1444+
OS << "static const llvm::MCSchedClassDesc " << Proc.ModelName
14571445
<< "SchedClasses[] = {\n";
14581446

14591447
// The first class is always invalid. We no way to distinguish it except by
@@ -1480,7 +1468,7 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
14801468
<< format("%2d", MCDesc.ReadAdvanceIdx) << ", "
14811469
<< MCDesc.NumReadAdvanceEntries << "}, // #" << SCIdx << '\n';
14821470
}
1483-
OS << "}; // " << PI->ModelName << "SchedClasses\n";
1471+
OS << "}; // " << Proc.ModelName << "SchedClasses\n";
14841472
}
14851473
}
14861474

@@ -1528,14 +1516,10 @@ void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
15281516

15291517
OS << " " << PM.Index << ", // Processor ID\n";
15301518
if (PM.hasInstrSchedModel())
1531-
OS << " " << PM.ModelName << "ProcResources"
1532-
<< ",\n"
1533-
<< " " << PM.ModelName << "SchedClasses"
1534-
<< ",\n"
1519+
OS << " " << PM.ModelName << "ProcResources" << ",\n"
1520+
<< " " << PM.ModelName << "SchedClasses" << ",\n"
15351521
<< " " << PM.ProcResourceDefs.size() + 1 << ",\n"
1536-
<< " "
1537-
<< (SchedModels.schedClassEnd() - SchedModels.schedClassBegin())
1538-
<< ",\n";
1522+
<< " " << SchedModels.schedClasses().size() << ",\n";
15391523
else
15401524
OS << " nullptr, nullptr, 0, 0,"
15411525
<< " // No instruction-level machine model.\n";
@@ -1747,7 +1731,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
17471731
? "if (CPUID == "
17481732
: "if (SchedModel->getProcessorID() == ");
17491733
OS << PI << ") ";
1750-
OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
1734+
OS << "{ // " << SchedModels.procModels()[PI].ModelName << '\n';
17511735
}
17521736

17531737
// Now emit transitions associated with processor PI.

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