@@ -106,7 +106,7 @@ class SubtargetEmitter {
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void emitStageAndOperandCycleData (
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raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
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void emitItineraries (raw_ostream &OS,
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- std::vector <std::vector<InstrItinerary>> & ProcItinLists);
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+ ArrayRef <std::vector<InstrItinerary>> ProcItinLists);
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unsigned emitRegisterFileTables (const CodeGenProcModel &ProcModel,
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raw_ostream &OS);
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void emitLoadStoreQueueInfo (const CodeGenProcModel &ProcModel,
@@ -477,7 +477,6 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
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// Emit functional units for all the itineraries.
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for (const CodeGenProcModel &ProcModel : SchedModels.procModels ()) {
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-
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if (!ItinsDefSet.insert (ProcModel.ItinsDef ).second )
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continue ;
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@@ -489,25 +488,23 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
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OS << " \n // Functional units for \" " << Name << " \"\n "
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<< " namespace " << Name << " FU {\n " ;
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- for (unsigned J = 0 , FUN = FUs. size (); J < FUN; ++J )
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- OS << " const InstrStage::FuncUnits " << FUs[J] ->getName ()
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- << " = 1ULL << " << J << " ;\n " ;
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+ for (const auto &[Idx, FU] : enumerate(FUs) )
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+ OS << " const InstrStage::FuncUnits " << FU ->getName () << " = 1ULL << "
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+ << Idx << " ;\n " ;
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OS << " } // end namespace " << Name << " FU\n " ;
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ConstRecVec BPs = ProcModel.ItinsDef ->getValueAsListOfDefs (" BP" );
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- if (! BPs.empty ()) {
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- OS << " \n // Pipeline forwarding paths for itineraries \" " << Name
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- << " \"\n "
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- << " namespace " << Name << " Bypass {\n " ;
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+ if (BPs.empty ())
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+ continue ;
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+ OS << " \n // Pipeline forwarding paths for itineraries \" " << Name << " \"\n "
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+ << " namespace " << Name << " Bypass {\n " ;
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- OS << " const unsigned NoBypass = 0;\n " ;
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- for (unsigned J = 0 , BPN = BPs.size (); J < BPN; ++J)
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- OS << " const unsigned " << BPs[J]->getName () << " = 1 << " << J
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- << " ;\n " ;
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+ OS << " const unsigned NoBypass = 0;\n " ;
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+ for (const auto &[Idx, BP] : enumerate(BPs))
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+ OS << " const unsigned " << BP->getName () << " = 1 << " << Idx << " ;\n " ;
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- OS << " } // end namespace " << Name << " Bypass\n " ;
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- }
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+ OS << " } // end namespace " << Name << " Bypass\n " ;
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}
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// Begin stages table
@@ -647,46 +644,39 @@ void SubtargetEmitter::emitStageAndOperandCycleData(
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// CodeGenSchedClass::Index.
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//
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void SubtargetEmitter::emitItineraries (
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- raw_ostream &OS, std::vector <std::vector<InstrItinerary>> & ProcItinLists) {
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+ raw_ostream &OS, ArrayRef <std::vector<InstrItinerary>> ProcItinLists) {
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// Multiple processor models may share an itinerary record. Emit it once.
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SmallPtrSet<const Record *, 8 > ItinsDefSet;
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- // For each processor's machine model
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- std::vector<std::vector<InstrItinerary>>::iterator ProcItinListsIter =
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- ProcItinLists.begin ();
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- for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin (),
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- PE = SchedModels.procModelEnd ();
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- PI != PE; ++PI, ++ProcItinListsIter) {
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-
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- const Record *ItinsDef = PI->ItinsDef ;
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+ for (const auto &[Proc, ItinList] :
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+ zip_equal (SchedModels.procModels (), ProcItinLists)) {
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+ const Record *ItinsDef = Proc.ItinsDef ;
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if (!ItinsDefSet.insert (ItinsDef).second )
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continue ;
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- // Get the itinerary list for the processor.
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- assert (ProcItinListsIter != ProcItinLists.end () && " bad iterator" );
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- std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
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-
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// Empty itineraries aren't referenced anywhere in the tablegen output
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// so don't emit them.
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if (ItinList.empty ())
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continue ;
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+ // Begin processor itinerary table
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OS << " \n " ;
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- OS << " static const llvm::InstrItinerary " ;
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+ OS << " static constexpr llvm::InstrItinerary " << ItinsDef->getName ()
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+ << " [] = {\n " ;
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- // Begin processor itinerary table
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- OS << ItinsDef-> getName () << " [] = { \n " ;
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+ ArrayRef<CodeGenSchedClass> ItinSchedClasses =
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+ SchedModels. schedClasses (). take_front (ItinList. size ()) ;
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// For each itinerary class in CodeGenSchedClass::Index order.
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- for (unsigned J = 0 , M = ItinList.size (); J < M; ++J) {
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- InstrItinerary &Intinerary = ItinList[J];
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-
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+ for (const auto &[Idx, Intinerary, SchedClass] :
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+ enumerate(ItinList, ItinSchedClasses)) {
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// Emit Itinerary in the form of
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- // { firstStage, lastStage, firstCycle, lastCycle } // index
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+ // { NumMicroOps, FirstStage, LastStage, FirstOperandCycle,
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+ // LastOperandCycle } // index class name
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OS << " { " << Intinerary.NumMicroOps << " , " << Intinerary.FirstStage
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<< " , " << Intinerary.LastStage << " , " << Intinerary.FirstOperandCycle
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- << " , " << Intinerary.LastOperandCycle << " }"
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- << " , // " << J << " " << SchedModels. getSchedClass (J) .Name << " \n " ;
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+ << " , " << Intinerary.LastOperandCycle << " }" << " , // " << Idx << " "
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+ << SchedClass .Name << " \n " ;
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}
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// End processor itinerary table
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OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
@@ -1442,18 +1432,16 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
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OS << " }; // " << Target << " ReadAdvanceTable\n " ;
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// Emit a SchedClass table for each processor.
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- for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin (),
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- PE = SchedModels.procModelEnd ();
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- PI != PE; ++PI) {
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- if (!PI->hasInstrSchedModel ())
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+ for (const auto &[Idx, Proc] : enumerate(SchedModels.procModels ())) {
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+ if (!Proc.hasInstrSchedModel ())
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continue ;
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std::vector<MCSchedClassDesc> &SCTab =
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- SchedTables.ProcSchedClasses [1 + (PI - SchedModels. procModelBegin ()) ];
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+ SchedTables.ProcSchedClasses [1 + Idx ];
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OS << " \n // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
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<< " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n " ;
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- OS << " static const llvm::MCSchedClassDesc " << PI-> ModelName
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+ OS << " static const llvm::MCSchedClassDesc " << Proc. ModelName
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<< " SchedClasses[] = {\n " ;
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// The first class is always invalid. We no way to distinguish it except by
@@ -1480,7 +1468,7 @@ void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
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<< format (" %2d" , MCDesc.ReadAdvanceIdx ) << " , "
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<< MCDesc.NumReadAdvanceEntries << " }, // #" << SCIdx << ' \n ' ;
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}
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- OS << " }; // " << PI-> ModelName << " SchedClasses\n " ;
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+ OS << " }; // " << Proc. ModelName << " SchedClasses\n " ;
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}
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}
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@@ -1528,14 +1516,10 @@ void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
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OS << " " << PM.Index << " , // Processor ID\n " ;
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if (PM.hasInstrSchedModel ())
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- OS << " " << PM.ModelName << " ProcResources"
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- << " ,\n "
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- << " " << PM.ModelName << " SchedClasses"
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- << " ,\n "
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+ OS << " " << PM.ModelName << " ProcResources" << " ,\n "
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+ << " " << PM.ModelName << " SchedClasses" << " ,\n "
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<< " " << PM.ProcResourceDefs .size () + 1 << " ,\n "
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- << " "
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- << (SchedModels.schedClassEnd () - SchedModels.schedClassBegin ())
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- << " ,\n " ;
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+ << " " << SchedModels.schedClasses ().size () << " ,\n " ;
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else
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OS << " nullptr, nullptr, 0, 0,"
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<< " // No instruction-level machine model.\n " ;
@@ -1747,7 +1731,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
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? " if (CPUID == "
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: " if (SchedModel->getProcessorID() == " );
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OS << PI << " ) " ;
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- OS << " { // " << ( SchedModels.procModelBegin () + PI)-> ModelName << ' \n ' ;
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+ OS << " { // " << SchedModels.procModels ()[PI]. ModelName << ' \n ' ;
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}
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// Now emit transitions associated with processor PI.
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