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-154
lines changed

10 files changed

+243
-154
lines changed

‎llvm/include/llvm/Target/Target.td

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,6 +1137,15 @@ class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
11371137
let MIOperandInfo = OpTypes;
11381138
}
11391139

1140+
// InstrDecoderOption - This class is used to provide some options to the
1141+
// TableGen DecoderEmitter backend.
1142+
class InstrDecoderOption<string ty, list<int> bws> {
1143+
string CPPType = ty; // C++ type for generating non-templated code.
1144+
list<int> Bitwidths = bws; // List of bitwidths supported by the above type.
1145+
1146+
assert !not(!empty(CPPType)), "CPP type cannot be empty";
1147+
assert !not(!empty(Bitwidths)), "Bitwidths cannot be empty";
1148+
}
11401149

11411150
// InstrInfo - This class should only be instantiated once to provide parameters
11421151
// which are global to the target machine.
@@ -1159,24 +1168,16 @@ class InstrInfo {
11591168
// This option is a temporary migration help. It will go away.
11601169
bit guessInstructionProperties = true;
11611170

1162-
// These properties, when set, opt into the non-templated variants of
1163-
// `decodeToMCInst` generated by TableGen DecoderEmitter backend. Using this
1164-
// option helps reduce the code size of the generated code as compared to the
1165-
// templated `decodeToMCInst` that is generated by default.
1166-
// For each index `I`, InsnCPPTypes[I] is a C++ type that will be used to
1167-
// generate a non-templated `decodeToMCInst`, and InstBitwidths[I] is a list
1168-
// instruction bitwidth(s) whose decoders will be included in the generated
1169-
// code.
1170-
list<string> InsnCPPTypes = [];
1171-
list<list<int>> InsnBitwidths = [];
1172-
assert !eq(!size(InsnCPPTypes), !size(InsnBitwidths)),
1173-
"The InsnCPPTypes and InsnBitwidths lists must be the same length";
1174-
1175-
// Make sure the InstCPPTypes, if not empty, does not contain empty strings.
1176-
assert !or(!empty(InsnCPPTypes), !empty(!filter(e, InsnCPPTypes, !empty(e)))),
1177-
"Entries in InstCPPTypes cannot be empty";
1178-
1179-
// Make sure that InsnBitwidths, if not empty, does not contain empty list.
1171+
// This is a list of instruction decoder options for this target. When non
1172+
// empty, it should list all the C++ types and associated bitwidths that this
1173+
// target intends to use to call the TableGen generated `decodeInstruction`
1174+
// function. If this list is empty, the decoder emitter will generate
1175+
// templated code. However, if a target intends to call this function with
1176+
// more than one `InsnType`, it may be beneficial to provide these decoder
1177+
// options to generate non-templated form of `decodeInstruction` and
1178+
// associated helper functions and avoid some code duplication in the
1179+
// `decodeToMCInst` function.
1180+
list<InstrDecoderOption> DecoderOptions = [];
11801181
}
11811182

11821183
// Standard Pseudo Instructions.

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,7 @@ include "AArch64SchedPredExynos.td"
4040
include "AArch64SchedPredNeoverse.td"
4141
include "AArch64Combine.td"
4242

43-
def AArch64InstrInfo : InstrInfo {
44-
// Opt-in into non-templated code for instruction decoder.
45-
let InsnCPPTypes = ["uint32_t"];
46-
let InsnBitwidths = [[32]];
47-
}
43+
def AArch64InstrInfo : InstrInfo;
4844

4945
//===----------------------------------------------------------------------===//
5046
// Named operands for MRS/MSR/TLBI/...

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1973,6 +1973,13 @@ def FeatureISAVersion12_Generic: FeatureSet<
19731973

19741974
def AMDGPUInstrInfo : InstrInfo {
19751975
let guessInstructionProperties = 1;
1976+
1977+
// Opt-in into non-templated code for instruction decoder.
1978+
let DecoderOptions = [
1979+
InstrDecoderOption<"uint32_t", [32]>,
1980+
InstrDecoderOption<"uint64_t", [64]>,
1981+
InstrDecoderOption<"DecoderUInt128", [96, 128]>,
1982+
];
19761983
}
19771984

19781985
def AMDGPUAsmParser : AsmParser {

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -591,7 +591,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
591591

592592
// Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
593593
// encodings
594-
if (isGFX11Plus() && Bytes.size() >= 12 ) {
594+
if (isGFX11Plus() && Bytes.size() >= 12) {
595595
DecoderUInt128 DecW = eat12Bytes(Bytes);
596596

597597
if (isGFX11() &&

‎llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,13 +111,13 @@ static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
111111
}
112112
#define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
113113

114-
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
114+
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, const APInt &Insn,
115115
uint64_t Address,
116116
const void *Decoder) {
117117
llvm_unreachable("unimplemented");
118118
}
119119

120-
static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn,
120+
static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, const APInt &Insn,
121121
uint64_t Address,
122122
const void *Decoder) {
123123
llvm_unreachable("unimplemented");

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,10 +85,6 @@ include "RISCVPfmCounters.td"
8585

8686
def RISCVInstrInfo : InstrInfo {
8787
let guessInstructionProperties = 0;
88-
89-
// Opt-in into non-templated code for instruction decoder.
90-
let InsnCPPTypes = ["uint64_t"];
91-
let InsnBitwidths = [[16, 32, 48]];
9288
}
9389

9490
def RISCVAsmParser : AsmParser {

‎llvm/test/TableGen/DecoderEmitterFnTable.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,11 +71,11 @@ def Inst3 : TestInstruction {
7171
let AsmString = "Inst3";
7272
}
7373

74-
// CHECK-LABEL: DecodeStatus decodeFn0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
75-
// CHECK-LABEL: DecodeStatus decodeFn1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
76-
// CHECK-LABEL: DecodeStatus decodeFn2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
77-
// CHECK-LABEL: DecodeStatus decodeFn3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
78-
// CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
74+
// CHECK-LABEL: DecodeStatus decodeFn0(DecodeStatus S, const InsnType &insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
75+
// CHECK-LABEL: DecodeStatus decodeFn1(DecodeStatus S, const InsnType &insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
76+
// CHECK-LABEL: DecodeStatus decodeFn2(DecodeStatus S, const InsnType &insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
77+
// CHECK-LABEL: DecodeStatus decodeFn3(DecodeStatus S, const InsnType &insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
78+
// CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, const InsnType &insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
7979
// CHECK: static constexpr DecodeFnTy decodeFnTable[]
8080
// CHECK-NEXT: decodeFn0,
8181
// CHECK-NEXT: decodeFn1,

‎llvm/test/TableGen/VarLenDecoder.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,12 @@ def FOO32 : MyVarInst<MemOp32> {
4747
);
4848
}
4949

50+
// Instruction length table
51+
// CHECK-LABEL: InstrLenTable
52+
// CHECK: 27,
53+
// CHECK-NEXT: 43,
54+
// CHECK-NEXT: };
55+
5056
// CHECK-SMALL: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ...
5157
// CHECK-SMALL-NEXT: /* 3 */ MCD::OPC_FilterValue, 8, 4, 0, // Skip to: 11
5258
// CHECK-SMALL-NEXT: /* 7 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16
@@ -81,12 +87,6 @@ def FOO32 : MyVarInst<MemOp32> {
8187
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
8288
// CHECK-NEXT: return S;
8389

84-
// Instruction length table
85-
// CHECK-LABEL: InstrLenTable
86-
// CHECK: 27,
87-
// CHECK-NEXT: 43,
88-
// CHECK-NEXT: };
89-
9090
// CHECK-LABEL: decodeInstruction
9191
// CHECK-LABEL: case MCD::OPC_ExtractField: {
9292
// CHECK: makeUp(insn, Start + Len);

‎llvm/test/TableGen/trydecode-emission.td

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,17 @@ def InstB : TestInstruction {
3434
let hasCompleteDecoder = 0;
3535
}
3636

37+
// CHECK-LABEL: decodeNumToSkip
38+
// CHECK-NEXT: unsigned NumToSkip = *Ptr++;
39+
// CHECK-NEXT: NumToSkip |= (*Ptr++) << 8;
40+
// CHECK-NEXT: return NumToSkip;
41+
42+
// CHECK-LARGE-LABEL: decodeNumToSkip
43+
// CHECK-LARGE-NEXT: unsigned NumToSkip = *Ptr++;
44+
// CHECK-LARGE-NEXT: NumToSkip |= (*Ptr++) << 8;
45+
// CHECK-LARGE-NEXT: NumToSkip |= (*Ptr++) << 16;
46+
// CHECK-LARGE-NEXT: return NumToSkip;
47+
3748
// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
3849
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0,
3950
// CHECK-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 6, 0, // Skip to: 17
@@ -43,10 +54,6 @@ def InstB : TestInstruction {
4354

4455
// CHECK: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; }
4556

46-
// CHECK: unsigned NumToSkip = *Ptr++;
47-
// CHECK-NEXT: NumToSkip |= (*Ptr++) << 8;
48-
// CHECK-NEXT: return NumToSkip;
49-
5057
// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
5158
// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0,
5259
// CHECK-LARGE-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 7, 0, 0, // Skip to: 19
@@ -55,8 +62,3 @@ def InstB : TestInstruction {
5562
// CHECK-LARGE-NEXT: /* 23 */ MCD::OPC_Fail,
5663

5764
// CHECK-LARGE: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; }
58-
59-
// CHECK-LARGE: unsigned NumToSkip = *Ptr++;
60-
// CHECK-LARGE-NEXT: NumToSkip |= (*Ptr++) << 8;
61-
// CHECK-LARGE-NEXT: NumToSkip |= (*Ptr++) << 16;
62-
// CHECK-LARGE-NEXT: return NumToSkip;

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