@@ -238,6 +238,7 @@ def F64RT : RegTyInfo<f64, Float64Regs, f64imm, fpimm>;
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def F16RT : RegTyInfo<f16, Int16Regs, f16imm, fpimm, supports_imm = 0>;
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def BF16RT : RegTyInfo<bf16, Int16Regs, bf16imm, fpimm, supports_imm = 0>;
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+ def F32X2RT : RegTyInfo<v2f32, Int64Regs, ?, ?, supports_imm = 0>;
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def F16X2RT : RegTyInfo<v2f16, Int32Regs, ?, ?, supports_imm = 0>;
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def BF16X2RT : RegTyInfo<v2bf16, Int32Regs, ?, ?, supports_imm = 0>;
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@@ -408,7 +409,18 @@ multiclass F3<string op_str, SDPatternOperator op_pat> {
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(ins Float32Regs:$a, f32imm:$b),
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op_str # ".f32 \t$dst, $a, $b;",
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[(set f32:$dst, (op_pat f32:$a, fpimm:$b))]>;
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-
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+ def f32x2rr_ftz :
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+ NVPTXInst<(outs Int64Regs:$dst),
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+ (ins Int64Regs:$a, Int64Regs:$b),
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+ op_str # ".ftz.f32x2 \t$dst, $a, $b;",
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+ [(set v2f32:$dst, (op_pat v2f32:$a, v2f32:$b))]>,
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+ Requires<[doF32FTZ, hasF32x2Instructions]>;
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+ def f32x2rr :
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+ NVPTXInst<(outs Int64Regs:$dst),
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+ (ins Int64Regs:$a, Int64Regs:$b),
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+ op_str # ".f32x2 \t$dst, $a, $b;",
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+ [(set v2f32:$dst, (op_pat v2f32:$a, v2f32:$b))]>,
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+ Requires<[hasF32x2Instructions]>;
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def f16rr_ftz :
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NVPTXInst<(outs Int16Regs:$dst),
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(ins Int16Regs:$a, Int16Regs:$b),
@@ -440,7 +452,6 @@ multiclass F3<string op_str, SDPatternOperator op_pat> {
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op_str # ".bf16 \t$dst, $a, $b;",
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[(set bf16:$dst, (op_pat bf16:$a, bf16:$b))]>,
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Requires<[hasBF16Math]>;
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-
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def bf16x2rr :
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NVPTXInst<(outs Int32Regs:$dst),
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(ins Int32Regs:$a, Int32Regs:$b),
@@ -1363,6 +1374,8 @@ defm BFMA16 : FMA<"fma.rn.bf16", BF16RT, [hasBF16Math]>;
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defm BFMA16x2 : FMA<"fma.rn.bf16x2", BF16X2RT, [hasBF16Math]>;
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defm FMA32_ftz : FMA<"fma.rn.ftz.f32", F32RT, [doF32FTZ]>;
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defm FMA32 : FMA<"fma.rn.f32", F32RT>;
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+ defm FMA32x2_ftz : FMA<"fma.rn.ftz.f32x2", F32X2RT, [doF32FTZ]>;
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+ defm FMA32x2 : FMA<"fma.rn.f32x2", F32X2RT>;
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defm FMA64 : FMA<"fma.rn.f64", F64RT>;
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// sin/cos
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