CodeGen: Remove redundant REQUIRES registered-target from backend tests (#147475)

These are already applied to all the tests in the target subdirectory

Author: arsenm

llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll

@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1  | FileCheck %s  --check-prefixes=CHECK,CHECK-SDAG
 ; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS
 
-; REQUIRES: asserts, aarch64-registered-target
+; REQUIRES: asserts
 
 ;; add
 define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {

llvm/test/CodeGen/AArch64/dump-schedule-trace.mir

@@ -32,7 +32,7 @@
 # RUN:  -sched-print-cycles=true -misched-dump-schedule-trace=true \
 # RUN:  2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL
 
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
 ---
 name: f
 tracksRegLiveness: true

llvm/test/CodeGen/AArch64/force-enable-intervals.mir

@@ -1,12 +1,12 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
 # RUN:  -misched-dump-reserved-cycles=true \
 # RUN:  -run-pass=machine-scheduler -debug-only=machine-scheduler \
-# RUN:  -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s 
+# RUN:  -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
 
 # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
 # RUN:  -misched-dump-reserved-cycles=true \
 # RUN:  -passes=machine-scheduler -debug-only=machine-scheduler \
-# RUN:  -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s 
+# RUN:  -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
 
 # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
 # RUN:  -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
@@ -18,7 +18,7 @@
 # RUN:  -passes=machine-scheduler -debug-only=machine-scheduler \
 # RUN:  -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s  --check-prefix=FORCE
 
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
 ---
 name: f
 tracksRegLiveness: true

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir

@@ -14,7 +14,7 @@
 # RUN:   -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
 # RUN: | FileCheck  %s
 
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
 
 --- |
   ; ModuleID = '../llvm-project/llvm/test/CodeGen/AArch64/aarch64-smull.failing.ll'

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir

@@ -12,7 +12,7 @@
 # RUN:  -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
 # RUN:  2>&1 | FileCheck %s
 
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
 ---
 name: f
 tracksRegLiveness: true
@@ -22,7 +22,7 @@ body:             |
     $x3 = ADDXrr $x0, $x0
     $x4 = ADDXrr $x1, $x1
     $x5 = ADDXrr $x2, $x2
-    
+
 # CHECK-LABEL: Before MISched:
 # CHECK-NEXT: # Machine code for function f: IsSSA, NoPHIs, TracksLiveness, NoVRegs
 # CHECK-EMPTY:

llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir

@@ -18,7 +18,7 @@
 # RUN:  -misched-prera-direction=topdown -sched-print-cycles=true \
 # RUN:  -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
 
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
 ---
 name: test
 tracksRegLiveness: true

llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir

@@ -1,7 +1,7 @@
 # RUN: llc -mtriple=thumbv7em-unknown-unknown -mcpu=cortex-m7 \
 # RUN:    -sched-model-force-enable-intervals \
 # RUN:    %s -run-pass=machine-scheduler -o - 2>&1 -debug | FileCheck %s
-# REQUIRES: arm-registered-target, asserts
+# REQUIRES: asserts
 
 # NOTE: Without the bugfix introduced in this code, the test below
 # would raise the assertion "A resource is being overwritten" from

llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll

@@ -1,5 +1,4 @@
 ; REQUIRES: asserts
-; REQUIRES: systemz-registered-target
 ; Used to fail with: LLVM ERROR: Error while trying to spill R5D from class ADDR64Bit: Cannot scavenge register without an emergency spill slot!
 
 

llvm/test/CodeGen/SystemZ/zos-ppa1.ll

@@ -1,5 +1,4 @@
 ; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
-; REQUIRES: systemz-registered-target
 
 ; CHECK: L#EPM_void_test_0: * @void_test
 ; CHECK: * XPLINK Routine Layout Entry

llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature
 ; RUN: opt -S --passes=expand-variadics --expand-variadics-override=lowering < %s | FileCheck %s
-; REQUIRES: webassembly-registered-target
 target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-n32:64-S128-ni:1:10:20"
 target triple = "wasm32-unknown-unknown"