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| 1 | +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=POWERPC_64 |
| 3 | +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=POWERPC_64LE |
| 4 | +// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=POWERPC_32 |
| 5 | + |
| 6 | +// POWERPC_64-LABEL: define dso_local signext i32 @test_Greater_than( |
| 7 | +// POWERPC_64-SAME: ptr noundef [[COLAUTHS:%.*]]) #[[ATTR0:[0-9]+]] { |
| 8 | +// POWERPC_64-NEXT: [[ENTRY:.*:]] |
| 9 | +// POWERPC_64-NEXT: [[COLAUTHS_ADDR:%.*]] = alloca ptr, align 8 |
| 10 | +// POWERPC_64-NEXT: [[RESULT:%.*]] = alloca i16, align 2 |
| 11 | +// POWERPC_64-NEXT: [[I:%.*]] = alloca i32, align 4 |
| 12 | +// POWERPC_64-NEXT: store ptr [[COLAUTHS]], ptr [[COLAUTHS_ADDR]], align 8 |
| 13 | +// POWERPC_64-NEXT: store i16 0, ptr [[RESULT]], align 2 |
| 14 | +// POWERPC_64-NEXT: store i32 0, ptr [[I]], align 4 |
| 15 | +// POWERPC_64-NEXT: br label %[[FOR_COND:.*]] |
| 16 | +// POWERPC_64: [[FOR_COND]]: |
| 17 | +// POWERPC_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 |
| 18 | +// POWERPC_64-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4 |
| 19 | +// POWERPC_64-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]] |
| 20 | +// POWERPC_64: [[FOR_BODY]]: |
| 21 | +// POWERPC_64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[COLAUTHS_ADDR]], align 8 |
| 22 | +// POWERPC_64-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 |
| 23 | +// POWERPC_64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 |
| 24 | +// POWERPC_64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 [[IDXPROM]] |
| 25 | +// POWERPC_64-NEXT: [[TMP3:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 |
| 26 | +// POWERPC_64-NEXT: [[CONV:%.*]] = zext i16 [[TMP3]] to i32 |
| 27 | +// POWERPC_64-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0 |
| 28 | +// POWERPC_64-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] |
| 29 | +// POWERPC_64: [[IF_THEN]]: |
| 30 | +// POWERPC_64-NEXT: [[TMP4:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 31 | +// POWERPC_64-NEXT: [[INC:%.*]] = add i16 [[TMP4]], 1 |
| 32 | +// POWERPC_64-NEXT: store i16 [[INC]], ptr [[RESULT]], align 2 |
| 33 | +// POWERPC_64-NEXT: br label %[[IF_END]] |
| 34 | +// POWERPC_64: [[IF_END]]: |
| 35 | +// POWERPC_64-NEXT: br label %[[FOR_INC:.*]] |
| 36 | +// POWERPC_64: [[FOR_INC]]: |
| 37 | +// POWERPC_64-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 |
| 38 | +// POWERPC_64-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP5]], 1 |
| 39 | +// POWERPC_64-NEXT: store i32 [[INC3]], ptr [[I]], align 4 |
| 40 | +// POWERPC_64-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] |
| 41 | +// POWERPC_64: [[FOR_END]]: |
| 42 | +// POWERPC_64-NEXT: [[TMP6:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 43 | +// POWERPC_64-NEXT: [[CONV4:%.*]] = zext i16 [[TMP6]] to i32 |
| 44 | +// POWERPC_64-NEXT: ret i32 [[CONV4]] |
| 45 | +// |
| 46 | +// POWERPC_64LE-LABEL: define dso_local signext i32 @test_Greater_than( |
| 47 | +// POWERPC_64LE-SAME: ptr noundef [[COLAUTHS:%.*]]) #[[ATTR0:[0-9]+]] { |
| 48 | +// POWERPC_64LE-NEXT: [[ENTRY:.*:]] |
| 49 | +// POWERPC_64LE-NEXT: [[COLAUTHS_ADDR:%.*]] = alloca ptr, align 8 |
| 50 | +// POWERPC_64LE-NEXT: [[RESULT:%.*]] = alloca i16, align 2 |
| 51 | +// POWERPC_64LE-NEXT: [[I:%.*]] = alloca i32, align 4 |
| 52 | +// POWERPC_64LE-NEXT: store ptr [[COLAUTHS]], ptr [[COLAUTHS_ADDR]], align 8 |
| 53 | +// POWERPC_64LE-NEXT: store i16 0, ptr [[RESULT]], align 2 |
| 54 | +// POWERPC_64LE-NEXT: store i32 0, ptr [[I]], align 4 |
| 55 | +// POWERPC_64LE-NEXT: br label %[[FOR_COND:.*]] |
| 56 | +// POWERPC_64LE: [[FOR_COND]]: |
| 57 | +// POWERPC_64LE-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 |
| 58 | +// POWERPC_64LE-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4 |
| 59 | +// POWERPC_64LE-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]] |
| 60 | +// POWERPC_64LE: [[FOR_BODY]]: |
| 61 | +// POWERPC_64LE-NEXT: [[TMP1:%.*]] = load ptr, ptr [[COLAUTHS_ADDR]], align 8 |
| 62 | +// POWERPC_64LE-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 |
| 63 | +// POWERPC_64LE-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 |
| 64 | +// POWERPC_64LE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 [[IDXPROM]] |
| 65 | +// POWERPC_64LE-NEXT: [[TMP3:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 |
| 66 | +// POWERPC_64LE-NEXT: [[CONV:%.*]] = zext i16 [[TMP3]] to i32 |
| 67 | +// POWERPC_64LE-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0 |
| 68 | +// POWERPC_64LE-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] |
| 69 | +// POWERPC_64LE: [[IF_THEN]]: |
| 70 | +// POWERPC_64LE-NEXT: [[TMP4:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 71 | +// POWERPC_64LE-NEXT: [[INC:%.*]] = add i16 [[TMP4]], 1 |
| 72 | +// POWERPC_64LE-NEXT: store i16 [[INC]], ptr [[RESULT]], align 2 |
| 73 | +// POWERPC_64LE-NEXT: br label %[[IF_END]] |
| 74 | +// POWERPC_64LE: [[IF_END]]: |
| 75 | +// POWERPC_64LE-NEXT: br label %[[FOR_INC:.*]] |
| 76 | +// POWERPC_64LE: [[FOR_INC]]: |
| 77 | +// POWERPC_64LE-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 |
| 78 | +// POWERPC_64LE-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP5]], 1 |
| 79 | +// POWERPC_64LE-NEXT: store i32 [[INC3]], ptr [[I]], align 4 |
| 80 | +// POWERPC_64LE-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] |
| 81 | +// POWERPC_64LE: [[FOR_END]]: |
| 82 | +// POWERPC_64LE-NEXT: [[TMP6:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 83 | +// POWERPC_64LE-NEXT: [[CONV4:%.*]] = zext i16 [[TMP6]] to i32 |
| 84 | +// POWERPC_64LE-NEXT: ret i32 [[CONV4]] |
| 85 | +// |
| 86 | +// POWERPC_32-LABEL: define dso_local i32 @test_Greater_than( |
| 87 | +// POWERPC_32-SAME: ptr noundef [[COLAUTHS:%.*]]) #[[ATTR0:[0-9]+]] { |
| 88 | +// POWERPC_32-NEXT: [[ENTRY:.*:]] |
| 89 | +// POWERPC_32-NEXT: [[COLAUTHS_ADDR:%.*]] = alloca ptr, align 4 |
| 90 | +// POWERPC_32-NEXT: [[RESULT:%.*]] = alloca i16, align 2 |
| 91 | +// POWERPC_32-NEXT: [[I:%.*]] = alloca i32, align 4 |
| 92 | +// POWERPC_32-NEXT: store ptr [[COLAUTHS]], ptr [[COLAUTHS_ADDR]], align 4 |
| 93 | +// POWERPC_32-NEXT: store i16 0, ptr [[RESULT]], align 2 |
| 94 | +// POWERPC_32-NEXT: store i32 0, ptr [[I]], align 4 |
| 95 | +// POWERPC_32-NEXT: br label %[[FOR_COND:.*]] |
| 96 | +// POWERPC_32: [[FOR_COND]]: |
| 97 | +// POWERPC_32-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 |
| 98 | +// POWERPC_32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4 |
| 99 | +// POWERPC_32-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]] |
| 100 | +// POWERPC_32: [[FOR_BODY]]: |
| 101 | +// POWERPC_32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[COLAUTHS_ADDR]], align 4 |
| 102 | +// POWERPC_32-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 |
| 103 | +// POWERPC_32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i32 [[TMP2]] |
| 104 | +// POWERPC_32-NEXT: [[TMP3:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 |
| 105 | +// POWERPC_32-NEXT: [[CONV:%.*]] = zext i16 [[TMP3]] to i32 |
| 106 | +// POWERPC_32-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0 |
| 107 | +// POWERPC_32-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] |
| 108 | +// POWERPC_32: [[IF_THEN]]: |
| 109 | +// POWERPC_32-NEXT: [[TMP4:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 110 | +// POWERPC_32-NEXT: [[INC:%.*]] = add i16 [[TMP4]], 1 |
| 111 | +// POWERPC_32-NEXT: store i16 [[INC]], ptr [[RESULT]], align 2 |
| 112 | +// POWERPC_32-NEXT: br label %[[IF_END]] |
| 113 | +// POWERPC_32: [[IF_END]]: |
| 114 | +// POWERPC_32-NEXT: br label %[[FOR_INC:.*]] |
| 115 | +// POWERPC_32: [[FOR_INC]]: |
| 116 | +// POWERPC_32-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 |
| 117 | +// POWERPC_32-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP5]], 1 |
| 118 | +// POWERPC_32-NEXT: store i32 [[INC3]], ptr [[I]], align 4 |
| 119 | +// POWERPC_32-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] |
| 120 | +// POWERPC_32: [[FOR_END]]: |
| 121 | +// POWERPC_32-NEXT: [[TMP6:%.*]] = load i16, ptr [[RESULT]], align 2 |
| 122 | +// POWERPC_32-NEXT: [[CONV4:%.*]] = zext i16 [[TMP6]] to i32 |
| 123 | +// POWERPC_32-NEXT: ret i32 [[CONV4]] |
| 124 | +// |
| 125 | +int test_Greater_than(unsigned short *colauths) { |
| 126 | + unsigned short result = 0; |
| 127 | + for (int i = 0; i < 4; i++) { |
| 128 | + if (colauths[i] > 0) { |
| 129 | + result++; |
| 130 | + } |
| 131 | + } |
| 132 | + return result; |
| 133 | +} |
| 134 | +//. |
| 135 | +// POWERPC_64: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} |
| 136 | +// POWERPC_64: [[META3]] = !{!"llvm.loop.mustprogress"} |
| 137 | +//. |
| 138 | +// POWERPC_64LE: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} |
| 139 | +// POWERPC_64LE: [[META3]] = !{!"llvm.loop.mustprogress"} |
| 140 | +//. |
| 141 | +// POWERPC_32: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} |
| 142 | +// POWERPC_32: [[META3]] = !{!"llvm.loop.mustprogress"} |
| 143 | +//. |
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