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AZero13AZero13
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[ARM] Copy SMAX(lhs, 0) and SMIN(lhs, 0) patterns from AArch64 to ARM (#146565)
They work on ARM too.
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4 files changed

+204
-3
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5519,6 +5519,24 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
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return DAG.getNode(ISD::OR, dl, VT, Shift, DAG.getConstant(1, dl, VT));
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}
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// Check for SMAX(lhs, 0) and SMIN(lhs, 0) patterns.
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// (SELECT_CC setgt, lhs, 0, lhs, 0) -> (BIC lhs, (SRA lhs, typesize-1))
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// (SELECT_CC setlt, lhs, 0, lhs, 0) -> (AND lhs, (SRA lhs, typesize-1))
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// Both require less instructions than compare and conditional select.
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if ((CC == ISD::SETGT || CC == ISD::SETLT) && LHS == TrueVal && RHSC &&
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RHSC->isZero() && CFVal && CFVal->isZero() &&
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LHS.getValueType() == RHS.getValueType()) {
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EVT VT = LHS.getValueType();
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SDValue Shift =
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DAG.getNode(ISD::SRA, dl, VT, LHS,
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DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
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if (CC == ISD::SETGT)
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Shift = DAG.getNOT(dl, Shift, VT);
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return DAG.getNode(ISD::AND, dl, VT, LHS, Shift);
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}
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}
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if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&

‎llvm/test/CodeGen/ARM/min-max-combine.ll

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a < %s | FileCheck %s --check-prefix=ARM
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; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB
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; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2
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; RUN: llc -mtriple=thumbv8.1m.main < %s | FileCheck %s --check-prefix=THUMBV8
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declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone
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define i8 @smaxi8_zero(i8 %a) {
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; ARM-LABEL: smaxi8_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: sxtb r0, r0
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; ARM-NEXT: bic r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smaxi8_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: sxtb r0, r0
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; THUMB-NEXT: asrs r1, r0, #31
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; THUMB-NEXT: bics r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smaxi8_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: sxtb r0, r0
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; THUMB2-NEXT: bic.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smaxi8_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: sxtb r0, r0
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; THUMBV8-NEXT: bic.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i8 @llvm.smax.i8(i8 %a, i8 0)
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ret i8 %c
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}
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declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone
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define i16 @smaxi16_zero(i16 %a) {
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; ARM-LABEL: smaxi16_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: sxth r0, r0
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; ARM-NEXT: bic r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smaxi16_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: sxth r0, r0
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; THUMB-NEXT: asrs r1, r0, #31
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; THUMB-NEXT: bics r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smaxi16_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: sxth r0, r0
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; THUMB2-NEXT: bic.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smaxi16_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: sxth r0, r0
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; THUMBV8-NEXT: bic.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i16 @llvm.smax.i16(i16 %a, i16 0)
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ret i16 %c
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}
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declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone
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define i32 @smaxi32_zero(i32 %a) {
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; ARM-LABEL: smaxi32_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: bic r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smaxi32_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: asrs r1, r0, #31
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; THUMB-NEXT: bics r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smaxi32_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: bic.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smaxi32_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: bic.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i32 @llvm.smax.i32(i32 %a, i32 0)
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ret i32 %c
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}
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; SMIN
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declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone
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define i8 @smini8_zero(i8 %a) {
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; ARM-LABEL: smini8_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: sxtb r0, r0
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; ARM-NEXT: and r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smini8_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: sxtb r1, r0
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; THUMB-NEXT: asrs r0, r1, #31
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; THUMB-NEXT: ands r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smini8_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: sxtb r0, r0
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; THUMB2-NEXT: and.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smini8_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: sxtb r0, r0
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; THUMBV8-NEXT: and.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i8 @llvm.smin.i8(i8 %a, i8 0)
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ret i8 %c
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}
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declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone
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define i16 @smini16_zero(i16 %a) {
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; ARM-LABEL: smini16_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: sxth r0, r0
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; ARM-NEXT: and r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smini16_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: sxth r1, r0
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; THUMB-NEXT: asrs r0, r1, #31
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; THUMB-NEXT: ands r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smini16_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: sxth r0, r0
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; THUMB2-NEXT: and.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smini16_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: sxth r0, r0
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; THUMBV8-NEXT: and.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i16 @llvm.smin.i16(i16 %a, i16 0)
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ret i16 %c
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}
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declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone
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define i32 @smini32_zero(i32 %a) {
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; ARM-LABEL: smini32_zero:
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; ARM: @ %bb.0:
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; ARM-NEXT: and r0, r0, r0, asr #31
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; ARM-NEXT: bx lr
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;
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; THUMB-LABEL: smini32_zero:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: asrs r1, r0, #31
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; THUMB-NEXT: ands r0, r1
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; THUMB-NEXT: bx lr
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;
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; THUMB2-LABEL: smini32_zero:
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; THUMB2: @ %bb.0:
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; THUMB2-NEXT: and.w r0, r0, r0, asr #31
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; THUMB2-NEXT: bx lr
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;
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; THUMBV8-LABEL: smini32_zero:
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; THUMBV8: @ %bb.0:
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; THUMBV8-NEXT: and.w r0, r0, r0, asr #31
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; THUMBV8-NEXT: bx lr
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%c = call i32 @llvm.smin.i32(i32 %a, i32 0)
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ret i32 %c
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}

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout-unknown-lanes.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ define arm_aapcs_vfpcc <4 x float> @arm_max_no_idx_f32_mve(ptr %pSrc, i32 %block
66
; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
9-
; CHECK-NEXT: subs r2, r1, #4
10-
; CHECK-NEXT: movw r3, #0
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: movt r3, #65408
1211
; CHECK-NEXT: vdup.32 q0, r3
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; CHECK-NEXT: dlstp.32 lr, r1

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@ define void @arm_cmplx_mag_squared_q15_mve(ptr %pSrc, ptr %pDst, i32 %blockSize)
55
; CHECK-LABEL: arm_cmplx_mag_squared_q15_mve:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
8-
; CHECK-NEXT: subs.w r3, r2, #8
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; CHECK-NEXT: dlstp.16 lr, r2
109
; CHECK-NEXT: .LBB0_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1

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