[Hexagon] aggr-copy-order.ll - regenerate test checks

Author: RKSimon

llvm/test/CodeGen/Hexagon/aggr-copy-order.ll

@@ -1,18 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=hexagon -mattr=-packets -hexagon-check-bank-conflict=0 < %s | FileCheck %s
-; Do not check stores. They undergo some optimizations in the DAG combiner
-; resulting in getting out of order. There is likely little that can be
-; done to keep the original order.
 
 target triple = "hexagon"
 
 %s.0 = type { i32, i32, i32 }
 
 ; Function Attrs: nounwind
 define void @f0(ptr %a0, ptr %a1) #0 {
+; CHECK-LABEL: f0:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = memw(r1+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#-8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r0+#0) = r2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r29+#0) = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = memw(r1+#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r29+#4) = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r0+#4) = r2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = memw(r1+#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r0+#8) = r2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-; CHECK: = memw({{.*}}+#0)
-; CHECK: = memw({{.*}}+#4)
-; CHECK: = memw({{.*}}+#8)
   %v0 = alloca ptr, align 4
   %v1 = alloca ptr, align 4
   store ptr %a0, ptr %v0, align 4