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[PHIElimination] Reuse existing COPY in predecessor basic block
The insertion point of COPY isn't always optimal and could eventually lead to a worse block layout, see the regression test. This change affects many architectures but the amount of total instructions in the test cases seems too be slightly lower.
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‎llvm/lib/CodeGen/PHIElimination.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -541,6 +541,7 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
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// Now loop over all of the incoming arguments, changing them to copy into the
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// IncomingReg register in the corresponding predecessor basic block.
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SmallPtrSet<MachineBasicBlock *, 8> MBBsInsertedInto;
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SmallVector<MachineInstr *, 8> InsertedCopies;
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for (int i = NumSrcs - 1; i >= 0; --i) {
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Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
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unsigned SrcSubReg = MPhi->getOperand(i * 2 + 1).getSubReg();
@@ -607,6 +608,7 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
607608
NewSrcInstr = TII->createPHISourceCopy(opBlock, InsertPos, nullptr,
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SrcReg, SrcSubReg, IncomingReg);
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}
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InsertedCopies.emplace_back(NewSrcInstr);
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}
611613

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// We only need to update the LiveVariables kill of SrcReg if this was the
@@ -730,6 +732,32 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
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}
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}
732734

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// Remove redundant COPY instruction chains, which were potentially added by
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// the code above. This can simplify the CFG which later on to prevent a
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// suboptimal block layout.
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for (MachineInstr *NewCopy : InsertedCopies) {
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if (NewCopy->isImplicitDef())
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continue;
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Register IncomingReg = NewCopy->getOperand(0).getReg();
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if (!IncomingReg.isVirtual())
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continue;
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Register SrcReg = NewCopy->getOperand(1).getReg();
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if (!MRI->hasOneNonDBGUse(SrcReg))
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continue;
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MachineInstr *DefMI = MRI->getUniqueVRegDef(SrcReg);
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if (!DefMI || !DefMI->isCopy() ||
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DefMI->getParent() != NewCopy->getParent())
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continue;
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const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg);
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const TargetRegisterClass *IncomingRC = MRI->getRegClass(IncomingReg);
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if (!IncomingRC->hasSuperClassEq(SrcRC))
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continue;
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MRI->replaceRegWith(SrcReg, IncomingReg);
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NewCopy->removeFromParent();
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if (LV)
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LV->getVarInfo(SrcReg).AliveBlocks.clear();
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}
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// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
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if (EliminateNow) {
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if (LIS)

‎llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir

Lines changed: 194 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,194 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -run-pass=livevars,phi-node-elimination -verify-machineinstrs -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
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# Verify that the original COPY in bb.1 is reappropriated as the PHI source in bb.2,
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# instead of creating a new COPY with the same source register.
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---
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name: copy_virtual_reg
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: copy_virtual_reg
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $nzcv, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:gpr32 = COPY killed $w0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK-NEXT: Bcc 8, %bb.2, implicit killed $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = COPY killed %a
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: %c:gpr32 = COPY killed [[DEF]]
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; CHECK-NEXT: dead %d:gpr32 = COPY killed %c
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bb.0:
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liveins: $nzcv, $w0
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%a:gpr32 = COPY $w0
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Bcc 8, %bb.2, implicit $nzcv
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bb.1:
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%b:gpr32 = COPY %a:gpr32
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bb.2:
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%c:gpr32 = PHI %b:gpr32, %bb.1, undef %undef:gpr32, %bb.0
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%d:gpr32 = COPY %c:gpr32
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...
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---
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name: copy_physical_reg
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: copy_physical_reg
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $nzcv, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK-NEXT: Bcc 8, %bb.2, implicit killed $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead $x0 = IMPLICIT_DEF implicit-def $w0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = COPY killed $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: dead %b:gpr32 = COPY killed [[DEF]]
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bb.0:
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liveins: $nzcv, $w0
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Bcc 8, %bb.2, implicit $nzcv
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bb.1:
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$x0 = IMPLICIT_DEF
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%a:gpr32 = COPY $w0
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bb.2:
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%b:gpr32 = PHI %a:gpr32, %bb.1, undef %undef:gpr32, %bb.0
67+
...
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---
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name: copy_to_dead
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: copy_to_dead
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $wzr, $xzr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
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; CHECK-NEXT: TBZW killed [[COPY]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK-NEXT: dead [[DEF3:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK-NEXT: B %bb.1
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bb.0:
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liveins: $wzr, $xzr
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99+
%9:gpr32 = COPY $wzr
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dead %5:gpr64 = COPY $xzr
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TBZW killed %9:gpr32, 0, %bb.2
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B %bb.1
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bb.1:
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successors: %bb.2(0x80000000); %bb.2(100.00%)
106+
107+
dead %1:gpr64 = PHI undef %3:gpr64, %bb.2, undef %5:gpr64, %bb.0
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dead %2:gpr64 = PHI undef %4:gpr64, %bb.2, undef %5:gpr64, %bb.0
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B %bb.2
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bb.2:
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successors: %bb.1(0x80000000); %bb.1(100.00%)
113+
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dead %3:gpr64 = PHI undef %1:gpr64, %bb.1, undef %5:gpr64, %bb.0
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dead %4:gpr64 = PHI undef %2:gpr64, %bb.1, undef %5:gpr64, %bb.0
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B %bb.1
117+
118+
...
119+
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---
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name: update_livevars
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: update_livevars
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0, $w1, $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY killed $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY killed $w1
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY1]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY3]]
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; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY killed [[COPY3]]
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; CHECK-NEXT: B %bb.1
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bb.0:
149+
successors: %bb.1
150+
liveins: $w0, $w1, $nzcv
151+
152+
%0:gpr32 = COPY killed $w0
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%1:gpr32 = COPY killed $w1
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B %bb.1
155+
156+
bb.1:
157+
successors: %bb.2, %bb.1
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liveins: $nzcv
159+
160+
%2:gpr32 = PHI %3, %bb.2, %1, %bb.0, %3, %bb.1
161+
%3:gpr32 = COPY %0
162+
Bcc 1, %bb.1, implicit $nzcv
163+
164+
bb.2:
165+
successors: %bb.1
166+
liveins: $nzcv
167+
168+
B %bb.1
169+
...
170+
171+
---
172+
name: copy_subreg
173+
tracksRegLiveness: true
174+
body: |
175+
; CHECK-LABEL: name: copy_subreg
176+
; CHECK: bb.0:
177+
; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY killed $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY killed [[COPY]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY1]].sub_32
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bb.0:
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successors: %bb.1
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liveins: $x0
188+
189+
%0:gpr64 = COPY killed $x0
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%1:gpr64 = COPY killed %0
191+
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bb.1:
193+
%2:gpr32 = PHI %1.sub_32, %bb.0
194+
...

‎llvm/test/CodeGen/PowerPC/vsx.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2487,7 +2487,7 @@ define double @test82(double %a, double %b, double %c, double %d) {
24872487
; CHECK-FISL-LABEL: test82:
24882488
; CHECK-FISL: # %bb.0: # %entry
24892489
; CHECK-FISL-NEXT: stfd f2, -16(r1) # 8-byte Folded Spill
2490-
; CHECK-FISL-NEXT: fmr f2, f1
2490+
; CHECK-FISL-NEXT: stfd f1, -8(r1) # 8-byte Folded Spill
24912491
; CHECK-FISL-NEXT: xscmpudp cr0, f3, f4
24922492
; CHECK-FISL-NEXT: stfd f2, -8(r1) # 8-byte Folded Spill
24932493
; CHECK-FISL-NEXT: beq cr0, .LBB67_2

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