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-122
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25 files changed

+120
-122
lines changed

‎llvm/include/llvm/TableGen/Record.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -803,6 +803,8 @@ class ListInit final : public TypedInit,
803803
size_t size() const { return NumElements; }
804804
bool empty() const { return NumElements == 0; }
805805

806+
std::vector<int64_t> getAsListOfInts() const;
807+
806808
const Init *getBit(unsigned Bit) const override {
807809
llvm_unreachable("Illegal bit reference off list");
808810
}

‎llvm/include/llvm/Target/Target.td

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,6 +1158,25 @@ class InstrInfo {
11581158
//
11591159
// This option is a temporary migration help. It will go away.
11601160
bit guessInstructionProperties = true;
1161+
1162+
// These properties, when set, opt into the non-templated variants of
1163+
// `decodeToMCInst` generated by TableGen DecoderEmitter backend. Using this
1164+
// option helps reduce the code size of the generated code as compared to the
1165+
// templated `decodeToMCInst` that is generated by default.
1166+
// For each index `I`, InsnCPPTypes[I] is a C++ type that will be used to
1167+
// generate a non-templated `decodeToMCInst`, and InstBitwidths[I] is a list
1168+
// instruction bitwidth(s) whose decoders will be included in the generated
1169+
// code.
1170+
list<string> InsnCPPTypes = [];
1171+
list<list<int>> InsnBitwidths = [];
1172+
assert !eq(!size(InsnCPPTypes), !size(InsnBitwidths)),
1173+
"The InsnCPPTypes and InsnBitwidths lists must be the same length";
1174+
1175+
// Make sure the InstCPPTypes, if not empty, does not contain empty strings.
1176+
assert !or(!empty(InsnCPPTypes), !empty(!filter(e, InsnCPPTypes, !empty(e)))),
1177+
"Entries in InstCPPTypes cannot be empty";
1178+
1179+
// Make sure that InsnBitwidths, if not empty, does not contain empty list.
11611180
}
11621181

11631182
// Standard Pseudo Instructions.

‎llvm/lib/TableGen/Record.cpp

Lines changed: 23 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -804,6 +804,15 @@ std::string ListInit::getAsString() const {
804804
return Result + "]";
805805
}
806806

807+
std::vector<int64_t> ListInit::getAsListOfInts() const {
808+
if (!isa<IntRecTy>(getElementType()))
809+
PrintFatalError("List does not contain integer values");
810+
std::vector<int64_t> Ints;
811+
for (const Init *I : getElements())
812+
Ints.push_back(cast<IntInit>(I)->getValue());
813+
return Ints;
814+
}
815+
807816
const Init *OpInit::getBit(unsigned Bit) const {
808817
if (getType() == BitRecTy::get(getRecordKeeper()))
809818
return this;
@@ -3119,32 +3128,26 @@ int64_t Record::getValueAsInt(StringRef FieldName) const {
31193128
std::vector<int64_t>
31203129
Record::getValueAsListOfInts(StringRef FieldName) const {
31213130
const ListInit *List = getValueAsListInit(FieldName);
3122-
std::vector<int64_t> Ints;
3123-
for (const Init *I : List->getElements()) {
3124-
if (const auto *II = dyn_cast<IntInit>(I))
3125-
Ints.push_back(II->getValue());
3126-
else
3127-
PrintFatalError(getLoc(),
3128-
Twine("Record `") + getName() + "', field `" + FieldName +
3129-
"' exists but does not have a list of ints value: " +
3130-
I->getAsString());
3131-
}
3132-
return Ints;
3131+
if (!isa<IntRecTy>(List->getElementType()))
3132+
PrintFatalError(getLoc(),
3133+
Twine("Record `") + getName() + "', field `" + FieldName +
3134+
"' exists but does not have a list of ints value: " +
3135+
List->getAsString());
3136+
return List->getAsListOfInts();
31333137
}
31343138

31353139
std::vector<StringRef>
31363140
Record::getValueAsListOfStrings(StringRef FieldName) const {
31373141
const ListInit *List = getValueAsListInit(FieldName);
3142+
if (!isa<StringRecTy>(List->getElementType()))
3143+
PrintFatalError(getLoc(),
3144+
Twine("Record `") + getName() + "', field `" + FieldName +
3145+
"' exists but does not have a list of string value: " +
3146+
List->getAsString());
3147+
31383148
std::vector<StringRef> Strings;
3139-
for (const Init *I : List->getElements()) {
3140-
if (const auto *SI = dyn_cast<StringInit>(I))
3141-
Strings.push_back(SI->getValue());
3142-
else
3143-
PrintFatalError(getLoc(),
3144-
Twine("Record `") + getName() + "', field `" + FieldName +
3145-
"' exists but does not have a list of strings value: " +
3146-
I->getAsString());
3147-
}
3149+
for (const Init *I : List->getElements())
3150+
Strings.push_back(cast<StringInit>(I)->getValue());
31483151
return Strings;
31493152
}
31503153

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,11 @@ include "AArch64SchedPredExynos.td"
4040
include "AArch64SchedPredNeoverse.td"
4141
include "AArch64Combine.td"
4242

43-
def AArch64InstrInfo : InstrInfo;
43+
def AArch64InstrInfo : InstrInfo {
44+
// Opt-in into non-templated code for instruction decoder.
45+
let InsnCPPTypes = ["uint32_t"];
46+
let InsnBitwidths = [[32]];
47+
}
4448

4549
//===----------------------------------------------------------------------===//
4650
// Named operands for MRS/MSR/TLBI/...

‎llvm/lib/Target/AArch64/CMakeLists.txt

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
88
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
99
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
10-
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
11-
-non-templated-decode-to-mcinst-type-spec=uint32_t:=32)
10+
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
1211
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
1312
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
1413
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner

‎llvm/lib/Target/AMDGPU/CMakeLists.txt

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,7 @@ tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler
10-
-non-templated-decode-to-mcinst-type-spec=uint32_t:=32
11-
-non-templated-decode-to-mcinst-type-spec=uint64_t:=64
12-
-non-templated-decode-to-mcinst-type-spec=DecoderUInt128:=96,128)
9+
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
1310
tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
1411
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
1512
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)

‎llvm/lib/Target/ARC/CMakeLists.txt

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,7 @@ set(LLVM_TARGET_DEFINITIONS ARC.td)
55
tablegen(LLVM ARCGenAsmWriter.inc -gen-asm-writer)
66
tablegen(LLVM ARCGenCallingConv.inc -gen-callingconv)
77
tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel)
8-
tablegen(LLVM ARCGenDisassemblerTables.inc -gen-disassembler
9-
-non-templated-decode-to-mcinst-type-spec=uint32_t:=16,32
10-
-non-templated-decode-to-mcinst-type-spec=uint64_t:=48,64)
8+
tablegen(LLVM ARCGenDisassemblerTables.inc -gen-disassembler)
119
tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info)
1210
tablegen(LLVM ARCGenRegisterInfo.inc -gen-register-info)
1311
tablegen(LLVM ARCGenSDNodeInfo.inc -gen-sd-node-info)

‎llvm/lib/Target/ARM/CMakeLists.txt

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,7 @@ tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler
10-
-non-templated-decode-to-mcinst-type-spec=uint16_t:=16
11-
-non-templated-decode-to-mcinst-type-spec=uint32_t:=32)
9+
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
1210
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
1311
tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
1412
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)

‎llvm/lib/Target/AVR/CMakeLists.txt

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
10-
-non-templated-decode-to-mcinst-type-spec=uint32_t:=16,32)
9+
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
1110
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
1211
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
1312
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)

‎llvm/lib/Target/BPF/CMakeLists.txt

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ tablegen(LLVM BPFGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler
10-
-non-templated-decode-to-mcinst-type-spec=uint64_t:=64)
9+
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler)
1110
tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
1211
tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
1312
tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)

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