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[AArch64] speculation-hardening-loads.ll - regenerate test checks
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‎llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

Lines changed: 108 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -1,156 +1,169 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s
23

34
define i128 @ldp_single_csdb(ptr %p) speculative_load_hardening {
5+
; CHECK-LABEL: ldp_single_csdb:
6+
; CHECK: // %bb.0: // %entry
7+
; CHECK-NEXT: ldp x8, x1, [x0]
8+
; CHECK-NEXT: cmp sp, #0
9+
; CHECK-NEXT: csetm x16, ne
10+
; CHECK-NEXT: and x8, x8, x16
11+
; CHECK-NEXT: and x1, x1, x16
12+
; CHECK-NEXT: csdb
13+
; CHECK-NEXT: mov x2, sp
14+
; CHECK-NEXT: mov x0, x8
15+
; CHECK-NEXT: and x2, x2, x16
16+
; CHECK-NEXT: mov sp, x2
17+
; CHECK-NEXT: ret
418
entry:
519
%0 = load i128, ptr %p, align 16
620
ret i128 %0
7-
; CHECK-LABEL: ldp_single_csdb
8-
; CHECK: ldp x8, x1, [x0]
9-
; CHECK-NEXT: cmp sp, #0
10-
; CHECK-NEXT: csetm x16, ne
11-
; CHECK-NEXT: and x8, x8, x16
12-
; CHECK-NEXT: and x1, x1, x16
13-
; CHECK-NEXT: csdb
14-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
15-
; CHECK-NEXT: mov x0, x8
16-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
17-
; CHECK-NEXT: mov sp, [[TMPREG]]
18-
; CHECK-NEXT: ret
1921
}
2022

23+
; Checking that the address loaded from is masked for a floating point load.
2124
define double @ld_double(ptr %p) speculative_load_hardening {
25+
; CHECK-LABEL: ld_double:
26+
; CHECK: // %bb.0: // %entry
27+
; CHECK-NEXT: cmp sp, #0
28+
; CHECK-NEXT: csetm x16, ne
29+
; CHECK-NEXT: and x0, x0, x16
30+
; CHECK-NEXT: csdb
31+
; CHECK-NEXT: ldr d0, [x0]
32+
; CHECK-NEXT: mov x0, sp
33+
; CHECK-NEXT: and x0, x0, x16
34+
; CHECK-NEXT: mov sp, x0
35+
; CHECK-NEXT: ret
2236
entry:
2337
%0 = load double, ptr %p, align 8
2438
ret double %0
25-
; Checking that the address loaded from is masked for a floating point load.
26-
; CHECK-LABEL: ld_double
27-
; CHECK: cmp sp, #0
28-
; CHECK-NEXT: csetm x16, ne
29-
; CHECK-NEXT: and x0, x0, x16
30-
; CHECK-NEXT: csdb
31-
; CHECK-NEXT: ldr d0, [x0]
32-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
33-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
34-
; CHECK-NEXT: mov sp, [[TMPREG]]
35-
; CHECK-NEXT: ret
3639
}
3740

41+
; Checking that the address loaded from is masked for a floating point load.
42+
; csdb instruction must occur before the add instruction with w8 as operand.
3843
define i32 @csdb_emitted_for_subreg_use(ptr %p, i32 %b) speculative_load_hardening {
44+
; CHECK-LABEL: csdb_emitted_for_subreg_use:
45+
; CHECK: // %bb.0: // %entry
46+
; CHECK-NEXT: cmp sp, #0
47+
; CHECK-NEXT: ldr x8, [x0]
48+
; CHECK-NEXT: csetm x16, ne
49+
; CHECK-NEXT: and x8, x8, x16
50+
; CHECK-NEXT: csdb
51+
; CHECK-NEXT: add w9, w1, w8
52+
; CHECK-NEXT: cmp x8, #0
53+
; CHECK-NEXT: csel w0, w1, w9, eq
54+
; CHECK-NEXT: mov x1, sp
55+
; CHECK-NEXT: and x1, x1, x16
56+
; CHECK-NEXT: mov sp, x1
57+
; CHECK-NEXT: ret
3958
entry:
4059
%X = load i64, ptr %p, align 8
4160
%X_trunc = trunc i64 %X to i32
4261
%add = add i32 %b, %X_trunc
4362
%iszero = icmp eq i64 %X, 0
4463
%ret = select i1 %iszero, i32 %b, i32 %add
4564
ret i32 %ret
46-
; Checking that the address loaded from is masked for a floating point load.
47-
; CHECK-LABEL: csdb_emitted_for_subreg_use
48-
; CHECK: cmp sp, #0
49-
; CHECK-NEXT: ldr x8, [x0]
50-
; CHECK-NEXT: csetm x16, ne
51-
; CHECK-NEXT: and x8, x8, x16
52-
; csdb instruction must occur before the add instruction with w8 as operand.
53-
; CHECK-NEXT: csdb
54-
; CHECK-NEXT: add w9, w1, w8
55-
; CHECK-NEXT: cmp x8, #0
56-
; CHECK-NEXT: csel w0, w1, w9, eq
57-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
58-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
59-
; CHECK-NEXT: mov sp, [[TMPREG]]
60-
; CHECK-NEXT: ret
6165
}
6266

67+
; Checking that the address loaded from is masked for a floating point load.
68+
; csdb instruction must occur before the add instruction with x8 as operand.
6369
define i64 @csdb_emitted_for_superreg_use(ptr %p, i64 %b) speculative_load_hardening {
70+
; CHECK-LABEL: csdb_emitted_for_superreg_use:
71+
; CHECK: // %bb.0: // %entry
72+
; CHECK-NEXT: cmp sp, #0
73+
; CHECK-NEXT: ldr w8, [x0]
74+
; CHECK-NEXT: csetm x16, ne
75+
; CHECK-NEXT: and w8, w8, w16
76+
; CHECK-NEXT: csdb
77+
; CHECK-NEXT: add x9, x1, x8
78+
; CHECK-NEXT: cmp w8, #0
79+
; CHECK-NEXT: csel x0, x1, x9, eq
80+
; CHECK-NEXT: mov x1, sp
81+
; CHECK-NEXT: and x1, x1, x16
82+
; CHECK-NEXT: mov sp, x1
83+
; CHECK-NEXT: ret
6484
entry:
6585
%X = load i32, ptr %p, align 4
6686
%X_ext = zext i32 %X to i64
6787
%add = add i64 %b, %X_ext
6888
%iszero = icmp eq i32 %X, 0
6989
%ret = select i1 %iszero, i64 %b, i64 %add
7090
ret i64 %ret
71-
; Checking that the address loaded from is masked for a floating point load.
72-
; CHECK-LABEL: csdb_emitted_for_superreg_use
73-
; CHECK: cmp sp, #0
74-
; CHECK-NEXT: ldr w8, [x0]
75-
; CHECK-NEXT: csetm x16, ne
76-
; CHECK-NEXT: and w8, w8, w16
77-
; csdb instruction must occur before the add instruction with x8 as operand.
78-
; CHECK-NEXT: csdb
79-
; CHECK-NEXT: add x9, x1, x8
80-
; CHECK-NEXT: cmp w8, #0
81-
; CHECK-NEXT: csel x0, x1, x9, eq
82-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
83-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
84-
; CHECK-NEXT: mov sp, [[TMPREG]]
85-
; CHECK-NEXT: ret
8691
}
8792

8893
define i64 @no_masking_with_full_control_flow_barriers(i64 %a, i64 %b, ptr %p) speculative_load_hardening {
89-
; CHECK-LABEL: no_masking_with_full_control_flow_barriers
90-
; CHECK: dsb sy
91-
; CHECK: isb
94+
; CHECK-LABEL: no_masking_with_full_control_flow_barriers:
95+
; CHECK: // %bb.0: // %entry
96+
; CHECK-NEXT: dsb sy
97+
; CHECK-NEXT: isb
98+
; CHECK-NEXT: ldr x8, [x2]
99+
; CHECK-NEXT: mov x17, x0
100+
; CHECK-NEXT: mov x16, x1
101+
; CHECK-NEXT: //APP
102+
; CHECK-NEXT: hint #12
103+
; CHECK-NEXT: //NO_APP
104+
; CHECK-NEXT: add x0, x8, x17
105+
; CHECK-NEXT: ret
92106
entry:
93107
%0 = tail call i64 asm "hint #12", "={x17},{x16},0"(i64 %b, i64 %a)
94108
%X = load i64, ptr %p, align 8
95109
%ret = add i64 %X, %0
96-
; CHECK-NOT: csdb
97-
; CHECK-NOT: and
98-
; CHECK: ret
99110
ret i64 %ret
100111
}
101112

102-
define void @f_implicitdef_vector_load(ptr %dst, ptr %src) speculative_load_hardening
103-
{
113+
define void @f_implicitdef_vector_load(ptr %dst, ptr %src) speculative_load_hardening {
114+
; CHECK-LABEL: f_implicitdef_vector_load:
115+
; CHECK: // %bb.0: // %entry
116+
; CHECK-NEXT: cmp sp, #0
117+
; CHECK-NEXT: csetm x16, ne
118+
; CHECK-NEXT: and x1, x1, x16
119+
; CHECK-NEXT: csdb
120+
; CHECK-NEXT: ldr d0, [x1]
121+
; CHECK-NEXT: mov v0.d[1], v0.d[0]
122+
; CHECK-NEXT: str q0, [x0]
123+
; CHECK-NEXT: mov x0, sp
124+
; CHECK-NEXT: and x0, x0, x16
125+
; CHECK-NEXT: mov sp, x0
126+
; CHECK-NEXT: ret
104127
entry:
105128
%0 = load <2 x i32>, ptr %src, align 8
106129
%shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
107130
store <4 x i32> %shuffle, ptr %dst, align 4
108131
ret void
109-
; CHECK-LABEL: f_implicitdef_vector_load
110-
; CHECK: cmp sp, #0
111-
; CHECK-NEXT: csetm x16, ne
112-
; CHECK-NEXT: and x1, x1, x16
113-
; CHECK-NEXT: csdb
114-
; CHECK-NEXT: ldr d0, [x1]
115-
; CHECK-NEXT: mov v0.d[1], v0.d[0]
116-
; CHECK-NEXT: str q0, [x0]
117-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
118-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
119-
; CHECK-NEXT: mov sp, [[TMPREG]]
120-
; CHECK-NEXT: ret
121132
}
122133

123134
define <2 x double> @f_usedefvectorload(ptr %a, ptr %b) speculative_load_hardening {
135+
; CHECK-LABEL: f_usedefvectorload:
136+
; CHECK: // %bb.0: // %entry
137+
; CHECK-NEXT: cmp sp, #0
138+
; CHECK-NEXT: csetm x16, ne
139+
; CHECK-NEXT: and x1, x1, x16
140+
; CHECK-NEXT: csdb
141+
; CHECK-NEXT: mov x0, sp
142+
; CHECK-NEXT: ldr d0, [x1]
143+
; CHECK-NEXT: and x0, x0, x16
144+
; CHECK-NEXT: mov sp, x0
145+
; CHECK-NEXT: ret
124146
entry:
125-
; CHECK-LABEL: f_usedefvectorload
126-
; CHECK: cmp sp, #0
127-
; CHECK-NEXT: csetm x16, ne
128-
; CHECK-NEXT: and x1, x1, x16
129-
; CHECK-NEXT: csdb
130-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
131-
; CHECK-NEXT: ldr d0, [x1]
132-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
133-
; CHECK-NEXT: mov sp, [[TMPREG]]
134-
; CHECK-NEXT: ret
135147
%0 = load double, ptr %b, align 16
136148
%vld1_lane = insertelement <2 x double> <double undef, double 0.000000e+00>, double %0, i32 0
137149
ret <2 x double> %vld1_lane
138150
}
139151

140152
define i32 @deadload() speculative_load_hardening uwtable {
153+
; CHECK-LABEL: deadload:
154+
; CHECK: // %bb.0: // %entry
155+
; CHECK-NEXT: cmp sp, #0
156+
; CHECK-NEXT: csetm x16, ne
157+
; CHECK-NEXT: sub sp, sp, #16
158+
; CHECK-NEXT: .cfi_def_cfa_offset 16
159+
; CHECK-NEXT: ldr w8, [sp, #12]
160+
; CHECK-NEXT: add sp, sp, #16
161+
; CHECK-NEXT: .cfi_def_cfa_offset 0
162+
; CHECK-NEXT: mov x0, sp
163+
; CHECK-NEXT: and x0, x0, x16
164+
; CHECK-NEXT: mov sp, x0
165+
; CHECK-NEXT: ret
141166
entry:
142-
; CHECK-LABEL: deadload
143-
; CHECK: cmp sp, #0
144-
; CHECK-NEXT: csetm x16, ne
145-
; CHECK-NEXT: sub sp, sp, #16
146-
; CHECK-NEXT: .cfi_def_cfa_offset 16
147-
; CHECK-NEXT: ldr w8, [sp, #12]
148-
; CHECK-NEXT: add sp, sp, #16
149-
; CHECK-NEXT: .cfi_def_cfa_offset 0
150-
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
151-
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
152-
; CHECK-NEXT: mov sp, [[TMPREG]]
153-
; CHECK-NEXT: ret
154167
%a = alloca i32, align 4
155168
%val = load volatile i32, ptr %a, align 4
156169
ret i32 undef

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