Skip to content

Commit 00a26f3

Browse files
BoyaoWang430BoyaoWang430
committed
[RISCV] Add optimization for memset inline
Optimize RISCV memset inline implementation based on the issue discussed in #144562.
1 parent 82c0a53 commit 00a26f3

26 files changed

+376
-228
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2019,9 +2019,9 @@ class LLVM_ABI TargetLoweringBase {
20192019
/// a result of memset, memcpy, and memmove lowering.
20202020
/// It returns EVT::Other if the type should be determined using generic
20212021
/// target-independent logic.
2022-
virtual EVT
2023-
getOptimalMemOpType(const MemOp &Op,
2024-
const AttributeList & /*FuncAttributes*/) const {
2022+
virtual EVT getOptimalMemOpType(const MemOp &Op,
2023+
const AttributeList & /*FuncAttributes*/,
2024+
LLVMContext *Context = nullptr) const {
20252025
return MVT::Other;
20262026
}
20272027

@@ -4108,10 +4108,11 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
41084108
/// Note that this is always the case when Limit is ~0.
41094109
/// It returns the types of the sequence of memory ops to perform
41104110
/// memset / memcpy by reference.
4111-
virtual bool
4112-
findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
4113-
const MemOp &Op, unsigned DstAS, unsigned SrcAS,
4114-
const AttributeList &FuncAttributes) const;
4111+
virtual bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
4112+
unsigned Limit, const MemOp &Op,
4113+
unsigned DstAS, unsigned SrcAS,
4114+
const AttributeList &FuncAttributes,
4115+
LLVMContext *Context = nullptr) const;
41154116

41164117
/// Check to see if the specified operand of the specified instruction is a
41174118
/// constant integer. If so, check to see if there are any bits set in the

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8334,7 +8334,7 @@ static SDValue getMemcpyLoadsAndStores(
83348334
*SrcAlign, isVol, CopyFromConstant);
83358335
if (!TLI.findOptimalMemOpLowering(
83368336
MemOps, Limit, Op, DstPtrInfo.getAddrSpace(),
8337-
SrcPtrInfo.getAddrSpace(), MF.getFunction().getAttributes()))
8337+
SrcPtrInfo.getAddrSpace(), MF.getFunction().getAttributes(), &C))
83388338
return SDValue();
83398339

83408340
if (DstAlignCanChange) {
@@ -8529,7 +8529,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
85298529
MemOp::Copy(Size, DstAlignCanChange, Alignment, *SrcAlign,
85308530
/*IsVolatile*/ true),
85318531
DstPtrInfo.getAddrSpace(), SrcPtrInfo.getAddrSpace(),
8532-
MF.getFunction().getAttributes()))
8532+
MF.getFunction().getAttributes(), &C))
85338533
return SDValue();
85348534

85358535
if (DstAlignCanChange) {
@@ -8634,6 +8634,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
86348634
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
86358635
std::vector<EVT> MemOps;
86368636
bool DstAlignCanChange = false;
8637+
LLVMContext &C = *DAG.getContext();
86378638
MachineFunction &MF = DAG.getMachineFunction();
86388639
MachineFrameInfo &MFI = MF.getFrameInfo();
86398640
bool OptSize = shouldLowerMemFuncForSize(MF, DAG);
@@ -8646,7 +8647,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
86468647
if (!TLI.findOptimalMemOpLowering(
86478648
MemOps, Limit,
86488649
MemOp::Set(Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
8649-
DstPtrInfo.getAddrSpace(), ~0u, MF.getFunction().getAttributes()))
8650+
DstPtrInfo.getAddrSpace(), ~0u, MF.getFunction().getAttributes(), &C))
86508651
return SDValue();
86518652

86528653
if (DstAlignCanChange) {

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -211,12 +211,13 @@ TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
211211

212212
bool TargetLowering::findOptimalMemOpLowering(
213213
std::vector<EVT> &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS,
214-
unsigned SrcAS, const AttributeList &FuncAttributes) const {
214+
unsigned SrcAS, const AttributeList &FuncAttributes,
215+
LLVMContext *Context) const {
215216
if (Limit != ~unsigned(0) && Op.isMemcpyWithFixedDstAlign() &&
216217
Op.getSrcAlign() < Op.getDstAlign())
217218
return false;
218219

219-
EVT VT = getOptimalMemOpType(Op, FuncAttributes);
220+
EVT VT = getOptimalMemOpType(Op, FuncAttributes, Context);
220221

221222
if (VT == MVT::Other) {
222223
// Use the largest integer type whose alignment constraints are satisfied.

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17587,7 +17587,8 @@ bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore(
1758717587
}
1758817588

1758917589
EVT AArch64TargetLowering::getOptimalMemOpType(
17590-
const MemOp &Op, const AttributeList &FuncAttributes) const {
17590+
const MemOp &Op, const AttributeList &FuncAttributes,
17591+
LLVMContext *Context) const {
1759117592
bool CanImplicitFloat = !FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat);
1759217593
bool CanUseNEON = Subtarget->hasNEON() && CanImplicitFloat;
1759317594
bool CanUseFP = Subtarget->hasFPARMv8() && CanImplicitFloat;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,8 @@ class AArch64TargetLowering : public TargetLowering {
233233

234234
bool shouldConsiderGEPOffsetSplit() const override;
235235

236-
EVT getOptimalMemOpType(const MemOp &Op,
237-
const AttributeList &FuncAttributes) const override;
236+
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes,
237+
LLVMContext *Context = nullptr) const override;
238238

239239
LLT getOptimalMemOpLLT(const MemOp &Op,
240240
const AttributeList &FuncAttributes) const override;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1982,8 +1982,9 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(
19821982
Alignment, Flags, IsFast);
19831983
}
19841984

1985-
EVT SITargetLowering::getOptimalMemOpType(
1986-
const MemOp &Op, const AttributeList &FuncAttributes) const {
1985+
EVT SITargetLowering::getOptimalMemOpType(const MemOp &Op,
1986+
const AttributeList &FuncAttributes,
1987+
LLVMContext *Context) const {
19871988
// FIXME: Should account for address space here.
19881989

19891990
// The default fallback uses the private pointer size as a guess for a type to

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -357,8 +357,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
357357
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
358358
unsigned *IsFast = nullptr) const override;
359359

360-
EVT getOptimalMemOpType(const MemOp &Op,
361-
const AttributeList &FuncAttributes) const override;
360+
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes,
361+
LLVMContext *Context = nullptr) const override;
362362

363363
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
364364

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19215,9 +19215,9 @@ bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
1921519215
return false;
1921619216
}
1921719217

19218-
19219-
EVT ARMTargetLowering::getOptimalMemOpType(
19220-
const MemOp &Op, const AttributeList &FuncAttributes) const {
19218+
EVT ARMTargetLowering::getOptimalMemOpType(const MemOp &Op,
19219+
const AttributeList &FuncAttributes,
19220+
LLVMContext *Context) const {
1922119221
// See if we can use NEON instructions for this...
1922219222
if ((Op.isMemcpy() || Op.isZeroMemset()) && Subtarget->hasNEON() &&
1922319223
!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {

‎llvm/lib/Target/ARM/ARMISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,8 @@ class VectorType;
473473
unsigned *Fast) const override;
474474

475475
EVT getOptimalMemOpType(const MemOp &Op,
476-
const AttributeList &FuncAttributes) const override;
476+
const AttributeList &FuncAttributes,
477+
LLVMContext *Context = nullptr) const override;
477478

478479
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
479480
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;

‎llvm/lib/Target/BPF/BPFISelLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,8 @@ class BPFTargetLowering : public TargetLowering {
114114
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
115115
SelectionDAG &DAG) const override;
116116

117-
EVT getOptimalMemOpType(const MemOp &Op,
118-
const AttributeList &FuncAttributes) const override {
117+
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes,
118+
LLVMContext *Context = nullptr) const override {
119119
return Op.size() >= 8 ? MVT::i64 : MVT::i32;
120120
}
121121

0 commit comments

Comments
 (0)