Documentation: teaching: lectures: interrupts.rst fix typos

Signed-off-by: etzl <erfanzamani3445@gmail.com>

Author: 3rt7

Documentation/teaching/lectures/interrupts.rst

@@ -28,12 +28,12 @@ What is an interrupt?
 
 An interrupt is an event that alters the normal execution flow of a
 program and can be generated by hardware devices or even by the CPU
-itself. When in interrupt occurs the current flow of execution is
+itself. When an interrupt occurs the current flow of execution is
 suspended and interrupt handler runs. After the interrupt handler runs
 the previous execution flow is resumed.
 
 Interrupts can be grouped into two categories based on the source of
-the interrupt. They can also be grouped in two other categories based
+the interrupt. They can also be grouped into two other categories based
 on the ability to postpone or temporarily disable the interrupt:
 
 .. slide:: Interrupts
@@ -48,13 +48,13 @@ on the ability to postpone or temporarily disable the interrupt:
 
      * can be ignored
 
-     * signalled via INT pin
+     * signaled via INT pin
 
    * **non-maskable**
 
      * cannot be ignored
 
-     * signalled via NMI pin
+     * signaled via NMI pin
 
 Synchronous interrupts, usually named exceptions, handle conditions detected by the
 processor itself in the course of executing an instruction. Divide by zero or
@@ -67,7 +67,7 @@ that a packet has arrived.
 Most interrupts are maskable, which means we can temporarily postpone
 running the interrupt handler when we disable the interrupt until the
 time the interrupt is re-enabled. However, there are a few critical
-interrupts that can not be disabled / postponed.
+interrupts that can not be disabled/postponed.
 
 Exceptions
 ----------
@@ -90,7 +90,7 @@ There are two sources for exceptions:
 
      - **int n**
 
-Processor detected exceptions are raised when an abornmal condition is
+Processor detected exceptions are raised when an abnormal condition is
 detected while executing an instruction.
 
 A fault is a type of exception that is reported before the execution of the
@@ -100,7 +100,7 @@ the program can re-execute the faulty instruction. (e.g page fault).
 
 A trap is a type of exception that is reported after the execution of the
 instruction in which the exception was detected. The saved EIP is the address
-of the instruction after the instuction that caused the trap. (e.g debug trap).
+of the instruction after the instruction that caused the trap. (e.g debug trap).
 
 Quiz: interrupt terminology
 ---------------------------
@@ -109,7 +109,7 @@ Quiz: interrupt terminology
    :inline-contents: True
    :level: 2
 
-   For each of the following term on the left select all the terms
+   For each of the following terms on the left select all the terms
    from right that best describe them.
 
    .. hlist::
@@ -159,7 +159,7 @@ Programmable Interrupt Controller
         |           |           |            |
         +-----------+           +------------+
 
-A device supporting interrupts has an output pin used for signalling an Interrupt ReQuest. IRQ
+A device supporting interrupts has an output pin used for signaling an Interrupt ReQuest. IRQ
 pins are connected to a device named Programmable Interrupt Controller (PIC) which is connected
 to CPU's INTR pin.
 
@@ -178,10 +178,10 @@ the current interrupt.
 
 .. note::
 
-   Once the interrupt is acknowledge by the CPU the interrupt
+   Once the interrupt is acknowledged by the CPU the interrupt
    controller can request another interrupt, regardless if the CPU
    finished handled the previous interrupt or not. Thus, depending on
-   how the OS controlls the CPU it is possible to have nested
+   how the OS controls the CPU it is possible to have nested
    interrupts.
 
 The interrupt controller allows each IRQ line to be individually
@@ -352,7 +352,7 @@ Quiz: hardware concepts
 Interrupt handling on the x86 architecture
 ==========================================
 
-This section will examine how interupts are handled by the CPU on the
+This section will examine how interrupts are handled by the CPU on the
 x86 architecture.
 
 Interrupt Descriptor Table
@@ -375,7 +375,7 @@ An IDT has the following characteristics:
    * processor locates IDT by the means of IDTR
 
 Below we can find Linux IRQ vector layout. The first 32 entries are reserved
-for exceptions, vector 128 is used for sycall interface and the rest are
+for exceptions, vector 128 is used for syscall interface and the rest are
 used mostly for hardware interrupts handlers.
 
 .. slide:: Linux IRQ vector layout
@@ -417,16 +417,16 @@ used mostly for hardware interrupts handlers.
 
 On x86 an IDT entry has 8 bytes and it is named gate. There can be 3 types of gates:
 
-  * interrupt gate, holds the address of an interupt or exception handler.
+  * interrupt gate, holds the address of an interrupt or exception handler.
     Jumping to the handler disables maskable interrupts (IF flag is cleared).
-  * trap gates, similar with an interrupt gate but it does not disable maskable
-    interrupts while jumping to interupt/exception handler.
+  * trap gates, similar to an interrupt gate but it does not disable maskable
+    interrupts while jumping to interrupt/exception handler.
   * task gates (not used in Linux)
 
-Lets have a look at several fields of an IDT entry:
+Let's have a look at several fields of an IDT entry:
 
    * segment selector, index into GDT/LDT to find the start of the code segment where
-     the interupt handlers resides
+     the interrupt handlers reside
    * offset, offset inside the code segment
    * T, represents the type of gate
    * DPL, minimum privilege required for using the segments content.
@@ -459,7 +459,7 @@ In order to find the interrupt handler address we first need to find the start
 address of the code segment where interrupt handler resides. For this we
 use the segment selector to index into GDT/LDT where we can find the corresponding
 segment descriptor. This will provide the start address kept in the 'base' field.
-Using base address and the offset we can now go at the start of the interrupt handler.
+Using base address and the offset we can now go to the start of the interrupt handler.
 
 
 .. slide:: Interrupt handler address
@@ -498,7 +498,7 @@ Using base address and the offset we can now go at the start of the interrupt ha
 Stack of interrupt handler
 --------------------------
 
-Similar with control transfer to a normal function, a control transfer
+Similar to control transfer to a normal function, a control transfer
 to an interrupt or exception handler uses the stack to store the 
 information needed for returning to the interrupted code.
 
@@ -552,7 +552,7 @@ Handling an interrupt request
 -----------------------------
 
 After an interrupt request has been generated the processor runs a sequence of
-events that eventually ends up with running the kernel interrupt handler:
+events that eventually end up with running the kernel interrupt handler:
 
 
 .. slide:: Handling an interrupt request
@@ -573,9 +573,9 @@ events that eventually ends up with running the kernel interrupt handler:
 Returning from an interrupt handler
 -----------------------------------
 
-Most architectures offers special instructions to clean-up the stack and resume
+Most architectures offer special instructions to clean up the stack and resume
 the execution after the interrupt handler has been executed. On x86 IRET is used
-to return from an interrupt handler. IRET is similar with RET except that IRET
+to return from an interrupt handler. IRET is similar to RET except that IRET
 increments ESP by extra four bytes (because of the flags on stack) and moves the
 saved flags into EFLAGS register.
 
@@ -585,7 +585,7 @@ To resume the execution after an interrupt the following sequence is used (x86):
    :inline-contents: True
    :level: 2
 
-   * pop the eror code (in case of an abort)
+   * pop the error code (in case of an abort)
    * call IRET
 
      * pops values from the stack and restore the following register: CS, EIP, EFLAGS
@@ -645,8 +645,8 @@ actions will also be performed (e.g. acknowledge the interrupt at the interrupt
 controller level). Local processor interrupts are disabled for the duration of
 this phase and continue to be disabled in the next phase.
 
-In the second phase all of the device drivers handler associated with this
-interrupt will be executed. At the end of this phase the interrupt controller's
+In the second phase, all of the device driver's handlers associated with this
+interrupt will be executed. At the end of this phase, the interrupt controller's
 "end of interrupt" method is called to allow the interrupt controller to
 reassert this interrupt. The local processor interrupts are enabled at this
 point.
@@ -657,12 +657,12 @@ point.
    devices and in this case it is said that the interrupt is
    shared. Usually, when using shared interrupts it is the
    responsibility of the device driver to determine if the interrupt
-   is target to it's device or not.
+   is target to its device or not.
 
 Finally, in the last phase of interrupt handling interrupt context deferrable
 actions will be run. These are also sometimes known as "bottom half" of the
 interrupt (the upper half being the part of the interrupt handling that runs
-with interrupts disabled). At this point interrupts are enabled on the local
+with interrupts disabled). At this point, interrupts are enabled on the local
 processor.
 
 .. slide:: Interrupt handling in Linux
@@ -697,7 +697,7 @@ ago in order to avoid increasingly complex solutions to stack
 overflows issues - allow just one level of nesting, allow multiple
 levels of nesting up to a certain kernel stack depth, etc.
 
-However it is still possible to have nesting between exceptions and
+However, it is still possible to have nesting between exceptions and
 interrupts but the rules are fairly restrictive:
 
 .. slide:: IRQ and exception nesting in Linux
@@ -771,7 +771,7 @@ interface and the network card buffer is full).
 
 Deferrable actions have APIs to: **initialize** an instance, **activate** or
 **schedule** the action and **mask/disable** and **unmask/enable** the execution
-of the callback function. The later is used for synchronization purposes between
+of the callback function. The latter is used for synchronization purposes between
 the callback function and other contexts.
 
 Typically the device driver will initialize the deferrable action
@@ -783,18 +783,18 @@ structure during the device instance initialization and will activate
    :level: 2
 
 
-    * Schedule callback functions to run a later time
+    * Schedule callback functions to run at a later time
 
     * Interrupt context deferrable actions
 
     * Process context deferrable actions
 
-    * APIs for initialization, scheduling and masking
+    * APIs for initialization, scheduling, and masking
 
 Soft IRQs
 ---------
 
-Soft IRQs is the term used for the low level mechanism that implements deferring
+Soft IRQs is the term used for the low-level mechanism that implements deferring
 work from interrupt handlers but that still runs in interrupt context.
 
 .. slide:: Soft IRQs