done

Author: mateuspinto

c/fsm/SimpleWriteOnExec.c

@@ -328,8 +328,8 @@ void FSM_SimpleWriteOnExec(CGRA * out_grid, InputEdgesVector * out_input, FILE *
                 }
             }
 
-            DEBUG_PRINT("[DEBUG] %u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), (double)(end - begin) / CLOCKS_PER_SEC, (double)debug_clock/swe_verilog_frequency);
-            fprintf(out_output, "%u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), (double)(end - begin) / CLOCKS_PER_SEC, (double)debug_clock/swe_verilog_frequency);
+            DEBUG_PRINT("[DEBUG] %u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), 1000000*(double)(end - begin) / CLOCKS_PER_SEC, 1000000*(double)debug_clock/swe_verilog_frequency);
+            fprintf(out_output, "%u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), 1000000*(double)(end - begin) / CLOCKS_PER_SEC, 1000000*(double)debug_clock/swe_verilog_frequency);
 
             return;
             break;

wrapper.py

@@ -61,9 +61,7 @@
 
     for i in range(12):
         for j in range(len(tables[i])):
-            if j==8 or j==9:
-                print(str(round(tables[i][j], 10)) + " ", end='')
-            elif j==7:
+            if j==7:
                 print(str(round(tables[i][j]*100, 2)) + "% ", end='')
             else:
                 print(str(round(tables[i][j],2)) + " ", end='')