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4 files changed

+17
-7
lines changed

4 files changed

+17
-7
lines changed

c/fsm/SimpleWriteOnExec.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,8 @@
2121

2222
#define swe_blacklist 15
2323

24+
#define swe_verilog_frequency 200000000 // In hz
25+
2426
void FSM_SimpleWriteOnExec(CGRA * out_grid, InputEdgesVector * out_input, FILE * out_output)
2527
{
2628
// Constants
@@ -68,6 +70,7 @@ void FSM_SimpleWriteOnExec(CGRA * out_grid, InputEdgesVector * out_input, FILE *
6870

6971
case swe_init:
7072
DEBUG_PRINT("swe_init\n");
73+
clock_t begin = clock();
7174

7275
next_inputIndex = 0;
7376

@@ -315,6 +318,7 @@ void FSM_SimpleWriteOnExec(CGRA * out_grid, InputEdgesVector * out_input, FILE *
315318
break;
316319
case swe_end:
317320
DEBUG_PRINT("swe_end\n");
321+
clock_t end = clock();
318322

319323
for (size_t i = 0; i < 4*out_grid->gridSize; i++)
320324
{
@@ -324,8 +328,8 @@ void FSM_SimpleWriteOnExec(CGRA * out_grid, InputEdgesVector * out_input, FILE *
324328
}
325329
}
326330

327-
DEBUG_PRINT("[DEBUG] %u, %u, %u, %f\n", debug_clock, debug_bl, debug_routed, (double)debug_usedOutputs/(out_grid->gridSize*4));
328-
fprintf(out_output, "%u, %u, %u, %f", debug_clock, debug_bl, debug_routed, (double)debug_usedOutputs/(out_grid->gridSize*4));
331+
DEBUG_PRINT("[DEBUG] %u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), (double)(end - begin) / CLOCKS_PER_SEC, (double)debug_clock/swe_verilog_frequency);
332+
fprintf(out_output, "%u, %u, %u, %f, %f, %f", debug_bl, debug_routed, debug_clock, (double)debug_usedOutputs/(out_grid->gridSize*4), (double)(end - begin) / CLOCKS_PER_SEC, (double)debug_clock/swe_verilog_frequency);
329333

330334
return;
331335
break;

c/fsm/SimpleWriteOnExec.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
#define SIMPLEWRITEONEXEC_H
33

44
#include "common.h"
5+
#include "time.h"
56

67
void FSM_SimpleWriteOnExec(CGRA * grid, InputEdgesVector * input, FILE * output);
78

c/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ int main(int argc, char const *argv[])
2323
gridFile = fopen(argv[1], "r");
2424
outputFile = fopen(argv[3], "w");
2525

26-
fprintf(outputFile, "size, empty, trivial, nontrivial, cycles, bl, routed, usage\n");
26+
fprintf(outputFile, "size, empty, trivial, nontrivial, routed, bl, cycles, usage, ctime, verilogtime\n");
2727

2828
while (!feof(gridFile))
2929
{

wrapper.py

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,16 @@
5757
acc=[]
5858
for csv in sorted(glob.glob(bench + "/*")):
5959
acc.append(pd.read_csv(csv))
60-
tables.append((pd.concat(acc).mean().round(decimals=2)))
60+
tables.append((pd.concat(acc).mean()))
6161

6262
for i in range(12):
63-
print(str(int(tables[i][0])) + " " + str(tables[i][1]) + " " + str(tables[i][2]) + " "
64-
+ str(tables[i][3]) + " " + str(tables[i][6]) + " " + str(tables[i][5]) + " " + str(tables[i][4]) + " " +
65-
str(int(round(tables[i][7]*100))) + "%")
63+
for j in range(len(tables[i])):
64+
if j==8 or j==9:
65+
print(str(round(tables[i][j], 10)) + " ", end='')
66+
elif j==7:
67+
print(str(round(tables[i][j]*100, 2)) + "% ", end='')
68+
else:
69+
print(str(round(tables[i][j],2)) + " ", end='')
70+
print()
6671
else:
6772
print("Error")

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