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1 | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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2 |
| -; RUN: llc -opaque-pointers=0 -fast-isel < %s | FileCheck %s |
| 2 | +; RUN: llc -fast-isel < %s | FileCheck %s |
3 | 3 | target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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4 | 4 | target triple = "thumbv7-apple-ios5.0.0"
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5 | 5 |
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6 | 6 | %0 = type opaque
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7 | 7 |
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8 |
| -; Make sure that the inline asm starts right after the call to bar. |
9 |
| -define void @test_inline_asm_sideeffect(%0* %call) { |
| 8 | +; Make sure that there are no unexpected instructions between the call to bar |
| 9 | +; and the inline asm. |
| 10 | +define void @test_inline_asm_sideeffect(ptr %call) { |
10 | 11 | ; CHECK-LABEL: test_inline_asm_sideeffect:
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11 | 12 | ; CHECK: @ %bb.0:
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12 | 13 | ; CHECK-NEXT: push {r4, r7, lr}
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13 | 14 | ; CHECK-NEXT: add r7, sp, #4
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14 | 15 | ; CHECK-NEXT: mov r4, r0
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15 | 16 | ; CHECK-NEXT: bl _bar
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| 17 | +; CHECK-NEXT: mov r0, r4 |
16 | 18 | ; CHECK-NEXT: @ InlineAsm Start
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17 | 19 | ; CHECK-NEXT: mov r7, r7 @ marker
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18 | 20 | ; CHECK-NEXT: @ InlineAsm End
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19 |
| -; CHECK-NEXT: movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) |
20 |
| -; CHECK-NEXT: movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) |
21 |
| -; CHECK-NEXT: LPC0_0: |
22 |
| -; CHECK-NEXT: add r0, pc |
23 |
| -; CHECK-NEXT: ldr r1, [r0] |
24 |
| -; CHECK-NEXT: mov r0, r4 |
25 |
| -; CHECK-NEXT: blx r1 |
| 21 | +; CHECK-NEXT: bl _foo |
26 | 22 | ; CHECK-NEXT: pop {r4, r7, pc}
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27 | 23 | call void @bar()
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28 | 24 | call void asm sideeffect "mov\09r7, r7\09\09@ marker", ""()
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29 |
| - %1 = call %0* bitcast (i8* (i8*)* @foo to %0* (%0*)*)(%0* %call) |
| 25 | + %1 = call ptr @foo(ptr %call) |
30 | 26 | ret void
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31 | 27 | }
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32 | 28 |
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33 |
| -declare i8* @foo(i8*) |
| 29 | +declare ptr @foo(ptr) |
34 | 30 | declare void @bar()
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