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21 | 21 | #define KVM_REG_ARM_STD_BMAP_BIT_MAX 0
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22 | 22 | #define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0
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23 | 23 | #define KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX 1
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| 24 | +#define KVM_REG_ARM_VENDOR_HYP_BMAP_2_BIT_MAX 1 |
| 25 | + |
| 26 | +#define KVM_REG_ARM_STD_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_STD_BMAP_BIT_MAX) |
| 27 | +#define KVM_REG_ARM_STD_HYP_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX) |
| 28 | +#define KVM_REG_ARM_VENDOR_HYP_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX) |
| 29 | +#define KVM_REG_ARM_VENDOR_HYP_BMAP_2_RESET_VAL 0 |
24 | 30 |
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25 | 31 | struct kvm_fw_reg_info {
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26 | 32 | uint64_t reg; /* Register definition */
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27 | 33 | uint64_t max_feat_bit; /* Bit that represents the upper limit of the feature-map */
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| 34 | + uint64_t reset_val; /* Reset value for the register */ |
28 | 35 | };
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29 | 36 |
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30 | 37 | #define FW_REG_INFO(r) \
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31 | 38 | { \
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32 | 39 | .reg = r, \
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33 | 40 | .max_feat_bit = r##_BIT_MAX, \
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| 41 | + .reset_val = r##_RESET_VAL \ |
34 | 42 | }
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35 | 43 |
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36 | 44 | static const struct kvm_fw_reg_info fw_reg_info[] = {
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37 | 45 | FW_REG_INFO(KVM_REG_ARM_STD_BMAP),
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38 | 46 | FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP),
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39 | 47 | FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP),
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| 48 | + FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP_2), |
40 | 49 | };
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41 | 50 |
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42 | 51 | enum test_stage {
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@@ -171,22 +180,39 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
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171 | 180 |
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172 | 181 | for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
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173 | 182 | const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
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| 183 | + uint64_t set_val; |
174 | 184 |
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175 |
| - /* First 'read' should be an upper limit of the features supported */ |
| 185 | + /* First 'read' should be the reset value for the reg */ |
176 | 186 | val = vcpu_get_reg(vcpu, reg_info->reg);
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177 |
| - TEST_ASSERT(val == FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), |
178 |
| - "Expected all the features to be set for reg: 0x%lx; expected: 0x%lx; read: 0x%lx", |
179 |
| - reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), val); |
| 187 | + TEST_ASSERT(val == reg_info->reset_val, |
| 188 | + "Unexpected reset value for reg: 0x%lx; expected: 0x%lx; read: 0x%lx", |
| 189 | + reg_info->reg, reg_info->reset_val, val); |
| 190 | + |
| 191 | + if (reg_info->reset_val) |
| 192 | + set_val = 0; |
| 193 | + else |
| 194 | + set_val = FW_REG_ULIMIT_VAL(reg_info->max_feat_bit); |
180 | 195 |
|
181 |
| - /* Test a 'write' by disabling all the features of the register map */ |
182 |
| - ret = __vcpu_set_reg(vcpu, reg_info->reg, 0); |
| 196 | + ret = __vcpu_set_reg(vcpu, reg_info->reg, set_val); |
183 | 197 | TEST_ASSERT(ret == 0,
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184 |
| - "Failed to clear all the features of reg: 0x%lx; ret: %d", |
185 |
| - reg_info->reg, errno); |
| 198 | + "Failed to %s all the features of reg: 0x%lx; ret: %d", |
| 199 | + (set_val ? "set" : "clear"), reg_info->reg, errno); |
186 | 200 |
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187 | 201 | val = vcpu_get_reg(vcpu, reg_info->reg);
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188 |
| - TEST_ASSERT(val == 0, |
189 |
| - "Expected all the features to be cleared for reg: 0x%lx", reg_info->reg); |
| 202 | + TEST_ASSERT(val == set_val, |
| 203 | + "Expected all the features to be %s for reg: 0x%lx", |
| 204 | + (set_val ? "set" : "cleared"), reg_info->reg); |
| 205 | + |
| 206 | + /* |
| 207 | + * If the reg has been set, clear it as test_fw_regs_after_vm_start() |
| 208 | + * expects it to be cleared. |
| 209 | + */ |
| 210 | + if (set_val) { |
| 211 | + ret = __vcpu_set_reg(vcpu, reg_info->reg, 0); |
| 212 | + TEST_ASSERT(ret == 0, |
| 213 | + "Failed to clear all the features of reg: 0x%lx; ret: %d", |
| 214 | + reg_info->reg, errno); |
| 215 | + } |
190 | 216 |
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191 | 217 | /*
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192 | 218 | * Test enabling a feature that's not supported.
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