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KVM: riscv: selftests: Align the trap information wiht pt_regs
The current exeception register structure in selftests are missing few registers (e.g stval). Instead of adding it manually, change the ex_regs to align with pt_regs to make it future proof. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
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6 files changed

+83
-76
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6 files changed

+83
-76
lines changed

‎tools/testing/selftests/kvm/include/riscv/processor.h

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,8 @@ static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext)
6060
return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext));
6161
}
6262

63-
struct ex_regs {
63+
struct pt_regs {
64+
unsigned long epc;
6465
unsigned long ra;
6566
unsigned long sp;
6667
unsigned long gp;
@@ -92,16 +93,19 @@ struct ex_regs {
9293
unsigned long t4;
9394
unsigned long t5;
9495
unsigned long t6;
95-
unsigned long epc;
96+
/* Supervisor/Machine CSRs */
9697
unsigned long status;
98+
unsigned long badaddr;
9799
unsigned long cause;
100+
/* a0 value before the syscall */
101+
unsigned long orig_a0;
98102
};
99103

100104
#define NR_VECTORS 2
101105
#define NR_EXCEPTIONS 32
102106
#define EC_MASK (NR_EXCEPTIONS - 1)
103107

104-
typedef void(*exception_handler_fn)(struct ex_regs *);
108+
typedef void(*exception_handler_fn)(struct pt_regs *);
105109

106110
void vm_init_vector_tables(struct kvm_vm *vm);
107111
void vcpu_init_vector_tables(struct kvm_vcpu *vcpu);

‎tools/testing/selftests/kvm/lib/riscv/handlers.S

Lines changed: 71 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -10,85 +10,88 @@
1010
#include <asm/csr.h>
1111

1212
.macro save_context
13-
addi sp, sp, (-8*34)
14-
sd x1, 0(sp)
15-
sd x2, 8(sp)
16-
sd x3, 16(sp)
17-
sd x4, 24(sp)
18-
sd x5, 32(sp)
19-
sd x6, 40(sp)
20-
sd x7, 48(sp)
21-
sd x8, 56(sp)
22-
sd x9, 64(sp)
23-
sd x10, 72(sp)
24-
sd x11, 80(sp)
25-
sd x12, 88(sp)
26-
sd x13, 96(sp)
27-
sd x14, 104(sp)
28-
sd x15, 112(sp)
29-
sd x16, 120(sp)
30-
sd x17, 128(sp)
31-
sd x18, 136(sp)
32-
sd x19, 144(sp)
33-
sd x20, 152(sp)
34-
sd x21, 160(sp)
35-
sd x22, 168(sp)
36-
sd x23, 176(sp)
37-
sd x24, 184(sp)
38-
sd x25, 192(sp)
39-
sd x26, 200(sp)
40-
sd x27, 208(sp)
41-
sd x28, 216(sp)
42-
sd x29, 224(sp)
43-
sd x30, 232(sp)
44-
sd x31, 240(sp)
13+
addi sp, sp, (-8*36)
14+
sd x1, 8(sp)
15+
sd x2, 16(sp)
16+
sd x3, 24(sp)
17+
sd x4, 32(sp)
18+
sd x5, 40(sp)
19+
sd x6, 48(sp)
20+
sd x7, 56(sp)
21+
sd x8, 64(sp)
22+
sd x9, 72(sp)
23+
sd x10, 80(sp)
24+
sd x11, 88(sp)
25+
sd x12, 96(sp)
26+
sd x13, 104(sp)
27+
sd x14, 112(sp)
28+
sd x15, 120(sp)
29+
sd x16, 128(sp)
30+
sd x17, 136(sp)
31+
sd x18, 144(sp)
32+
sd x19, 152(sp)
33+
sd x20, 160(sp)
34+
sd x21, 168(sp)
35+
sd x22, 176(sp)
36+
sd x23, 184(sp)
37+
sd x24, 192(sp)
38+
sd x25, 200(sp)
39+
sd x26, 208(sp)
40+
sd x27, 216(sp)
41+
sd x28, 224(sp)
42+
sd x29, 232(sp)
43+
sd x30, 240(sp)
44+
sd x31, 248(sp)
4545
csrr s0, CSR_SEPC
4646
csrr s1, CSR_SSTATUS
47-
csrr s2, CSR_SCAUSE
48-
sd s0, 248(sp)
47+
csrr s2, CSR_STVAL
48+
csrr s3, CSR_SCAUSE
49+
sd s0, 0(sp)
4950
sd s1, 256(sp)
5051
sd s2, 264(sp)
52+
sd s3, 272(sp)
5153
.endm
5254

5355
.macro restore_context
56+
ld s3, 272(sp)
5457
ld s2, 264(sp)
5558
ld s1, 256(sp)
56-
ld s0, 248(sp)
57-
csrw CSR_SCAUSE, s2
59+
ld s0, 0(sp)
60+
csrw CSR_SCAUSE, s3
5861
csrw CSR_SSTATUS, s1
5962
csrw CSR_SEPC, s0
60-
ld x31, 240(sp)
61-
ld x30, 232(sp)
62-
ld x29, 224(sp)
63-
ld x28, 216(sp)
64-
ld x27, 208(sp)
65-
ld x26, 200(sp)
66-
ld x25, 192(sp)
67-
ld x24, 184(sp)
68-
ld x23, 176(sp)
69-
ld x22, 168(sp)
70-
ld x21, 160(sp)
71-
ld x20, 152(sp)
72-
ld x19, 144(sp)
73-
ld x18, 136(sp)
74-
ld x17, 128(sp)
75-
ld x16, 120(sp)
76-
ld x15, 112(sp)
77-
ld x14, 104(sp)
78-
ld x13, 96(sp)
79-
ld x12, 88(sp)
80-
ld x11, 80(sp)
81-
ld x10, 72(sp)
82-
ld x9, 64(sp)
83-
ld x8, 56(sp)
84-
ld x7, 48(sp)
85-
ld x6, 40(sp)
86-
ld x5, 32(sp)
87-
ld x4, 24(sp)
88-
ld x3, 16(sp)
89-
ld x2, 8(sp)
90-
ld x1, 0(sp)
91-
addi sp, sp, (8*34)
63+
ld x31, 248(sp)
64+
ld x30, 240(sp)
65+
ld x29, 232(sp)
66+
ld x28, 224(sp)
67+
ld x27, 216(sp)
68+
ld x26, 208(sp)
69+
ld x25, 200(sp)
70+
ld x24, 192(sp)
71+
ld x23, 184(sp)
72+
ld x22, 176(sp)
73+
ld x21, 168(sp)
74+
ld x20, 160(sp)
75+
ld x19, 152(sp)
76+
ld x18, 144(sp)
77+
ld x17, 136(sp)
78+
ld x16, 128(sp)
79+
ld x15, 120(sp)
80+
ld x14, 112(sp)
81+
ld x13, 104(sp)
82+
ld x12, 96(sp)
83+
ld x11, 88(sp)
84+
ld x10, 80(sp)
85+
ld x9, 72(sp)
86+
ld x8, 64(sp)
87+
ld x7, 56(sp)
88+
ld x6, 48(sp)
89+
ld x5, 40(sp)
90+
ld x4, 32(sp)
91+
ld x3, 24(sp)
92+
ld x2, 16(sp)
93+
ld x1, 8(sp)
94+
addi sp, sp, (8*36)
9295
.endm
9396

9497
.balign 4

‎tools/testing/selftests/kvm/lib/riscv/processor.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,7 @@ struct handlers {
402402
exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS];
403403
};
404404

405-
void route_exception(struct ex_regs *regs)
405+
void route_exception(struct pt_regs *regs)
406406
{
407407
struct handlers *handlers = (struct handlers *)exception_handlers;
408408
int vector = 0, ec;

‎tools/testing/selftests/kvm/riscv/arch_timer.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515

1616
static int timer_irq = IRQ_S_TIMER;
1717

18-
static void guest_irq_handler(struct ex_regs *regs)
18+
static void guest_irq_handler(struct pt_regs *regs)
1919
{
2020
uint64_t xcnt, xcnt_diff_us, cmp;
2121
unsigned int intid = regs->cause & ~CAUSE_IRQ_FLAG;

‎tools/testing/selftests/kvm/riscv/ebreak_test.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ static void guest_code(void)
2727
GUEST_DONE();
2828
}
2929

30-
static void guest_breakpoint_handler(struct ex_regs *regs)
30+
static void guest_breakpoint_handler(struct pt_regs *regs)
3131
{
3232
WRITE_ONCE(sw_bp_addr, regs->epc);
3333
regs->epc += 4;

‎tools/testing/selftests/kvm/riscv/sbi_pmu_test.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,7 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags)
128128
"Unable to stop counter %ld error %ld\n", counter, ret.error);
129129
}
130130

131-
static void guest_illegal_exception_handler(struct ex_regs *regs)
131+
static void guest_illegal_exception_handler(struct pt_regs *regs)
132132
{
133133
__GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL,
134134
"Unexpected exception handler %lx\n", regs->cause);
@@ -138,7 +138,7 @@ static void guest_illegal_exception_handler(struct ex_regs *regs)
138138
regs->epc += 4;
139139
}
140140

141-
static void guest_irq_handler(struct ex_regs *regs)
141+
static void guest_irq_handler(struct pt_regs *regs)
142142
{
143143
unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG;
144144
struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva;

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