@@ -1100,132 +1100,23 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
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set_sysreg_masks (kvm , HCRX_EL2 , res0 , res1 );
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/* HFG[RW]TR_EL2 */
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- res0 = res1 = 0 ;
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- if (!(kvm_vcpu_has_feature (kvm , KVM_ARM_VCPU_PTRAUTH_ADDRESS ) &&
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- kvm_vcpu_has_feature (kvm , KVM_ARM_VCPU_PTRAUTH_GENERIC )))
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- res0 |= (HFGRTR_EL2_APDAKey | HFGRTR_EL2_APDBKey |
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- HFGRTR_EL2_APGAKey | HFGRTR_EL2_APIAKey |
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- HFGRTR_EL2_APIBKey );
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- if (!kvm_has_feat (kvm , ID_AA64MMFR1_EL1 , LO , IMP ))
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- res0 |= (HFGRTR_EL2_LORC_EL1 | HFGRTR_EL2_LOREA_EL1 |
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- HFGRTR_EL2_LORID_EL1 | HFGRTR_EL2_LORN_EL1 |
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- HFGRTR_EL2_LORSA_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64PFR0_EL1 , CSV2 , CSV2_2 ) &&
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- !kvm_has_feat (kvm , ID_AA64PFR1_EL1 , CSV2_frac , CSV2_1p2 ))
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- res0 |= (HFGRTR_EL2_SCXTNUM_EL1 | HFGRTR_EL2_SCXTNUM_EL0 );
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- if (!kvm_has_feat (kvm , ID_AA64PFR0_EL1 , GIC , IMP ))
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- res0 |= HFGRTR_EL2_ICC_IGRPENn_EL1 ;
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- if (!kvm_has_feat (kvm , ID_AA64PFR0_EL1 , RAS , IMP ))
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- res0 |= (HFGRTR_EL2_ERRIDR_EL1 | HFGRTR_EL2_ERRSELR_EL1 |
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- HFGRTR_EL2_ERXFR_EL1 | HFGRTR_EL2_ERXCTLR_EL1 |
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- HFGRTR_EL2_ERXSTATUS_EL1 | HFGRTR_EL2_ERXMISCn_EL1 |
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- HFGRTR_EL2_ERXPFGF_EL1 | HFGRTR_EL2_ERXPFGCTL_EL1 |
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- HFGRTR_EL2_ERXPFGCDN_EL1 | HFGRTR_EL2_ERXADDR_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64ISAR1_EL1 , LS64 , LS64_ACCDATA ))
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- res0 |= HFGRTR_EL2_nACCDATA_EL1 ;
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- if (!kvm_has_feat (kvm , ID_AA64PFR1_EL1 , GCS , IMP ))
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- res0 |= (HFGRTR_EL2_nGCS_EL0 | HFGRTR_EL2_nGCS_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64PFR1_EL1 , SME , IMP ))
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- res0 |= (HFGRTR_EL2_nSMPRI_EL1 | HFGRTR_EL2_nTPIDR2_EL0 );
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- if (!kvm_has_feat (kvm , ID_AA64PFR1_EL1 , THE , IMP ))
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- res0 |= HFGRTR_EL2_nRCWMASK_EL1 ;
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- if (!kvm_has_s1pie (kvm ))
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- res0 |= (HFGRTR_EL2_nPIRE0_EL1 | HFGRTR_EL2_nPIR_EL1 );
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- if (!kvm_has_s1poe (kvm ))
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- res0 |= (HFGRTR_EL2_nPOR_EL0 | HFGRTR_EL2_nPOR_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64MMFR3_EL1 , S2POE , IMP ))
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- res0 |= HFGRTR_EL2_nS2POR_EL1 ;
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- if (!kvm_has_feat (kvm , ID_AA64MMFR3_EL1 , AIE , IMP ))
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- res0 |= (HFGRTR_EL2_nMAIR2_EL1 | HFGRTR_EL2_nAMAIR2_EL1 );
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- set_sysreg_masks (kvm , HFGRTR_EL2 , res0 | hfgrtr_masks .res0 , res1 );
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- set_sysreg_masks (kvm , HFGWTR_EL2 , res0 | hfgwtr_masks .res0 , res1 );
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+ get_reg_fixed_bits (kvm , HFGRTR_EL2 , & res0 , & res1 );
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+ set_sysreg_masks (kvm , HFGRTR_EL2 , res0 , res1 );
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+ get_reg_fixed_bits (kvm , HFGWTR_EL2 , & res0 , & res1 );
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+ set_sysreg_masks (kvm , HFGWTR_EL2 , res0 , res1 );
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/* HDFG[RW]TR_EL2 */
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- res0 = res1 = 0 ;
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , DoubleLock , IMP ))
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- res0 |= HDFGRTR_EL2_OSDLR_EL1 ;
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , PMUVer , IMP ))
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- res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 |
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- HDFGRTR_EL2_PMCCFILTR_EL0 | HDFGRTR_EL2_PMCCNTR_EL0 |
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- HDFGRTR_EL2_PMCNTEN | HDFGRTR_EL2_PMINTEN |
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- HDFGRTR_EL2_PMOVS | HDFGRTR_EL2_PMSELR_EL0 |
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- HDFGRTR_EL2_PMMIR_EL1 | HDFGRTR_EL2_PMUSERENR_EL0 |
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- HDFGRTR_EL2_PMCEIDn_EL0 );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , PMSVer , IMP ))
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- res0 |= (HDFGRTR_EL2_PMBLIMITR_EL1 | HDFGRTR_EL2_PMBPTR_EL1 |
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- HDFGRTR_EL2_PMBSR_EL1 | HDFGRTR_EL2_PMSCR_EL1 |
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- HDFGRTR_EL2_PMSEVFR_EL1 | HDFGRTR_EL2_PMSFCR_EL1 |
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- HDFGRTR_EL2_PMSICR_EL1 | HDFGRTR_EL2_PMSIDR_EL1 |
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- HDFGRTR_EL2_PMSIRR_EL1 | HDFGRTR_EL2_PMSLATFR_EL1 |
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- HDFGRTR_EL2_PMBIDR_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , TraceVer , IMP ))
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- res0 |= (HDFGRTR_EL2_TRC | HDFGRTR_EL2_TRCAUTHSTATUS |
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- HDFGRTR_EL2_TRCAUXCTLR | HDFGRTR_EL2_TRCCLAIM |
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- HDFGRTR_EL2_TRCCNTVRn | HDFGRTR_EL2_TRCID |
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- HDFGRTR_EL2_TRCIMSPECn | HDFGRTR_EL2_TRCOSLSR |
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- HDFGRTR_EL2_TRCPRGCTLR | HDFGRTR_EL2_TRCSEQSTR |
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- HDFGRTR_EL2_TRCSSCSRn | HDFGRTR_EL2_TRCSTATR |
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- HDFGRTR_EL2_TRCVICTLR );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , TraceBuffer , IMP ))
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- res0 |= (HDFGRTR_EL2_TRBBASER_EL1 | HDFGRTR_EL2_TRBIDR_EL1 |
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- HDFGRTR_EL2_TRBLIMITR_EL1 | HDFGRTR_EL2_TRBMAR_EL1 |
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- HDFGRTR_EL2_TRBPTR_EL1 | HDFGRTR_EL2_TRBSR_EL1 |
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- HDFGRTR_EL2_TRBTRG_EL1 );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , BRBE , IMP ))
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- res0 |= (HDFGRTR_EL2_nBRBIDR | HDFGRTR_EL2_nBRBCTL |
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- HDFGRTR_EL2_nBRBDATA );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , PMSVer , V1P2 ))
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- res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1 ;
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- set_sysreg_masks (kvm , HDFGRTR_EL2 , res0 | hdfgrtr_masks .res0 , res1 );
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-
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- /* Reuse the bits from the read-side and add the write-specific stuff */
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , PMUVer , IMP ))
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- res0 |= (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0 );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , TraceVer , IMP ))
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- res0 |= HDFGWTR_EL2_TRCOSLAR ;
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , TraceFilt , IMP ))
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- res0 |= HDFGWTR_EL2_TRFCR_EL1 ;
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- set_sysreg_masks (kvm , HFGWTR_EL2 , res0 | hdfgwtr_masks .res0 , res1 );
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+ get_reg_fixed_bits (kvm , HDFGRTR_EL2 , & res0 , & res1 );
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+ set_sysreg_masks (kvm , HDFGRTR_EL2 , res0 , res1 );
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+ get_reg_fixed_bits (kvm , HDFGWTR_EL2 , & res0 , & res1 );
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+ set_sysreg_masks (kvm , HDFGWTR_EL2 , res0 , res1 );
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/* HFGITR_EL2 */
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- res0 = hfgitr_masks .res0 ;
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- res1 = HFGITR_EL2_RES1 ;
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- if (!kvm_has_feat (kvm , ID_AA64ISAR1_EL1 , DPB , DPB2 ))
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- res0 |= HFGITR_EL2_DCCVADP ;
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- if (!kvm_has_feat (kvm , ID_AA64MMFR1_EL1 , PAN , PAN2 ))
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- res0 |= (HFGITR_EL2_ATS1E1RP | HFGITR_EL2_ATS1E1WP );
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- if (!kvm_has_feat (kvm , ID_AA64ISAR0_EL1 , TLB , OS ))
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- res0 |= (HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS |
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- HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS |
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- HFGITR_EL2_TLBIVAALE1OS | HFGITR_EL2_TLBIVALE1OS |
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- HFGITR_EL2_TLBIVAAE1OS | HFGITR_EL2_TLBIASIDE1OS |
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- HFGITR_EL2_TLBIVAE1OS | HFGITR_EL2_TLBIVMALLE1OS );
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- if (!kvm_has_feat (kvm , ID_AA64ISAR0_EL1 , TLB , RANGE ))
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- res0 |= (HFGITR_EL2_TLBIRVAALE1 | HFGITR_EL2_TLBIRVALE1 |
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- HFGITR_EL2_TLBIRVAAE1 | HFGITR_EL2_TLBIRVAE1 |
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- HFGITR_EL2_TLBIRVAALE1IS | HFGITR_EL2_TLBIRVALE1IS |
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- HFGITR_EL2_TLBIRVAAE1IS | HFGITR_EL2_TLBIRVAE1IS |
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- HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS |
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- HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS );
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- if (!kvm_has_feat (kvm , ID_AA64ISAR1_EL1 , SPECRES , IMP ))
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- res0 |= (HFGITR_EL2_CFPRCTX | HFGITR_EL2_DVPRCTX |
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- HFGITR_EL2_CPPRCTX );
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- if (!kvm_has_feat (kvm , ID_AA64DFR0_EL1 , BRBE , IMP ))
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- res0 |= (HFGITR_EL2_nBRBINJ | HFGITR_EL2_nBRBIALL );
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- if (!kvm_has_feat (kvm , ID_AA64PFR1_EL1 , GCS , IMP ))
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- res0 |= (HFGITR_EL2_nGCSPUSHM_EL1 | HFGITR_EL2_nGCSSTR_EL1 |
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- HFGITR_EL2_nGCSEPP );
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- if (!kvm_has_feat (kvm , ID_AA64ISAR1_EL1 , SPECRES , COSP_RCTX ))
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- res0 |= HFGITR_EL2_COSPRCTX ;
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- if (!kvm_has_feat (kvm , ID_AA64ISAR2_EL1 , ATS1A , IMP ))
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- res0 |= HFGITR_EL2_ATS1E1A ;
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+ get_reg_fixed_bits (kvm , HFGITR_EL2 , & res0 , & res1 );
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set_sysreg_masks (kvm , HFGITR_EL2 , res0 , res1 );
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/* HAFGRTR_EL2 - not a lot to see here */
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- res0 = hafgrtr_masks .res0 ;
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- res1 = HAFGRTR_EL2_RES1 ;
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- if (!kvm_has_feat (kvm , ID_AA64PFR0_EL1 , AMU , V1P1 ))
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- res0 |= ~(res0 | res1 );
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+ get_reg_fixed_bits (kvm , HAFGRTR_EL2 , & res0 , & res1 );
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set_sysreg_masks (kvm , HAFGRTR_EL2 , res0 , res1 );
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/* TCR2_EL2 */
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