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Marc Zyngier
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KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits
Similarly to other registers, describe which HCR_EL2 bit depends on which feature, and use this to compute the RES0 status of these bits. Signed-off-by: Marc Zyngier <maz@kernel.org>
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+79
-39
lines changed

2 files changed

+79
-39
lines changed

‎arch/arm64/kvm/config.c

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,8 @@ struct reg_bits_to_feat_map {
7777
#define FEAT_THE ID_AA64PFR1_EL1, THE, IMP
7878
#define FEAT_SME ID_AA64PFR1_EL1, SME, IMP
7979
#define FEAT_GCS ID_AA64PFR1_EL1, GCS, IMP
80+
#define FEAT_LS64 ID_AA64ISAR1_EL1, LS64, LS64
81+
#define FEAT_LS64_V ID_AA64ISAR1_EL1, LS64, LS64_V
8082
#define FEAT_LS64_ACCDATA ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA
8183
#define FEAT_RAS ID_AA64PFR0_EL1, RAS, IMP
8284
#define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP
@@ -90,6 +92,16 @@ struct reg_bits_to_feat_map {
9092
#define FEAT_PAN2 ID_AA64MMFR1_EL1, PAN, PAN2
9193
#define FEAT_DPB2 ID_AA64ISAR1_EL1, DPB, DPB2
9294
#define FEAT_AMUv1 ID_AA64PFR0_EL1, AMU, IMP
95+
#define FEAT_CMOW ID_AA64MMFR1_EL1, CMOW, IMP
96+
#define FEAT_D128 ID_AA64MMFR3_EL1, D128, IMP
97+
#define FEAT_DoubleFault2 ID_AA64PFR1_EL1, DF2, IMP
98+
#define FEAT_FPMR ID_AA64PFR2_EL1, FPMR, IMP
99+
#define FEAT_MOPS ID_AA64ISAR2_EL1, MOPS, IMP
100+
#define FEAT_NMI ID_AA64PFR1_EL1, NMI, IMP
101+
#define FEAT_SCTLR2 ID_AA64MMFR3_EL1, SCTLRX, IMP
102+
#define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP
103+
#define FEAT_TCR2 ID_AA64MMFR3_EL1, TCRX, IMP
104+
#define FEAT_XS ID_AA64ISAR1_EL1, XS, IMP
93105

94106
static bool feat_rasv1p1(struct kvm *kvm)
95107
{
@@ -110,6 +122,35 @@ static bool feat_pauth(struct kvm *kvm)
110122
return kvm_has_pauth(kvm, PAuth);
111123
}
112124

125+
static bool feat_pauth_lr(struct kvm *kvm)
126+
{
127+
return kvm_has_pauth(kvm, PAuth_LR);
128+
}
129+
130+
static bool feat_aderr(struct kvm *kvm)
131+
{
132+
return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) &&
133+
kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SDERR, FEAT_ADERR));
134+
}
135+
136+
static bool feat_anerr(struct kvm *kvm)
137+
{
138+
return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) &&
139+
kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SNERR, FEAT_ANERR));
140+
}
141+
142+
static bool feat_sme_smps(struct kvm *kvm)
143+
{
144+
/*
145+
* Revists this if KVM ever supports SME -- this really should
146+
* look at the guest's view of SMIDR_EL1. Funnily enough, this
147+
* is not captured in the JSON file, but only as a note in the
148+
* ARM ARM.
149+
*/
150+
return (kvm_has_feat(kvm, FEAT_SME) &&
151+
(read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS));
152+
}
153+
113154
static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = {
114155
NEEDS_FEAT(HFGRTR_EL2_nAMAIR2_EL1 |
115156
HFGRTR_EL2_nMAIR2_EL1,
@@ -494,6 +535,35 @@ static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = {
494535
FEAT_AMUv1),
495536
};
496537

538+
static const struct reg_bits_to_feat_map hcrx_feat_map[] = {
539+
NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr),
540+
NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR),
541+
NEEDS_FEAT(HCRX_EL2_GCSEn, FEAT_GCS),
542+
NEEDS_FEAT(HCRX_EL2_EnIDCP128, FEAT_SYSREG128),
543+
NEEDS_FEAT(HCRX_EL2_EnSDERR, feat_aderr),
544+
NEEDS_FEAT(HCRX_EL2_TMEA, FEAT_DoubleFault2),
545+
NEEDS_FEAT(HCRX_EL2_EnSNERR, feat_anerr),
546+
NEEDS_FEAT(HCRX_EL2_D128En, FEAT_D128),
547+
NEEDS_FEAT(HCRX_EL2_PTTWI, FEAT_THE),
548+
NEEDS_FEAT(HCRX_EL2_SCTLR2En, FEAT_SCTLR2),
549+
NEEDS_FEAT(HCRX_EL2_TCR2En, FEAT_TCR2),
550+
NEEDS_FEAT(HCRX_EL2_MSCEn |
551+
HCRX_EL2_MCE2,
552+
FEAT_MOPS),
553+
NEEDS_FEAT(HCRX_EL2_CMOW, FEAT_CMOW),
554+
NEEDS_FEAT(HCRX_EL2_VFNMI |
555+
HCRX_EL2_VINMI |
556+
HCRX_EL2_TALLINT,
557+
FEAT_NMI),
558+
NEEDS_FEAT(HCRX_EL2_SMPME, feat_sme_smps),
559+
NEEDS_FEAT(HCRX_EL2_FGTnXS |
560+
HCRX_EL2_FnXS,
561+
FEAT_XS),
562+
NEEDS_FEAT(HCRX_EL2_EnASR, FEAT_LS64_V),
563+
NEEDS_FEAT(HCRX_EL2_EnALS, FEAT_LS64),
564+
NEEDS_FEAT(HCRX_EL2_EnAS0, FEAT_LS64_ACCDATA),
565+
};
566+
497567
static void __init check_feat_map(const struct reg_bits_to_feat_map *map,
498568
int map_size, u64 res0, const char *str)
499569
{
@@ -521,6 +591,8 @@ void __init check_feature_map(void)
521591
hdfgwtr_masks.res0, hdfgwtr_masks.str);
522592
check_feat_map(hafgrtr_feat_map, ARRAY_SIZE(hafgrtr_feat_map),
523593
hafgrtr_masks.res0, hafgrtr_masks.str);
594+
check_feat_map(hcrx_feat_map, ARRAY_SIZE(hcrx_feat_map),
595+
__HCRX_EL2_RES0, "HCRX_EL2");
524596
}
525597

526598
static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map)
@@ -656,6 +728,12 @@ void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *r
656728
*res0 |= hafgrtr_masks.res0;
657729
*res1 = HAFGRTR_EL2_RES1;
658730
break;
731+
case HCRX_EL2:
732+
*res0 = compute_res0_bits(kvm, hcrx_feat_map,
733+
ARRAY_SIZE(hcrx_feat_map), 0, 0);
734+
*res0 |= __HCRX_EL2_RES0;
735+
*res1 = __HCRX_EL2_RES1;
736+
break;
659737
default:
660738
WARN_ON_ONCE(1);
661739
*res0 = *res1 = 0;

‎arch/arm64/kvm/nested.c

Lines changed: 1 addition & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,45 +1058,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
10581058
set_sysreg_masks(kvm, HCR_EL2, res0, res1);
10591059

10601060
/* HCRX_EL2 */
1061-
res0 = __HCRX_EL2_RES0;
1062-
res1 = __HCRX_EL2_RES1;
1063-
if (!kvm_has_feat(kvm, ID_AA64ISAR3_EL1, PACM, TRIVIAL_IMP))
1064-
res0 |= HCRX_EL2_PACMEn;
1065-
if (!kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP))
1066-
res0 |= HCRX_EL2_EnFPM;
1067-
if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP))
1068-
res0 |= HCRX_EL2_GCSEn;
1069-
if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, SYSREG_128, IMP))
1070-
res0 |= HCRX_EL2_EnIDCP128;
1071-
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, DEV_ASYNC))
1072-
res0 |= (HCRX_EL2_EnSDERR | HCRX_EL2_EnSNERR);
1073-
if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, DF2, IMP))
1074-
res0 |= HCRX_EL2_TMEA;
1075-
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP))
1076-
res0 |= HCRX_EL2_D128En;
1077-
if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP))
1078-
res0 |= HCRX_EL2_PTTWI;
1079-
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SCTLRX, IMP))
1080-
res0 |= HCRX_EL2_SCTLR2En;
1081-
if (!kvm_has_tcr2(kvm))
1082-
res0 |= HCRX_EL2_TCR2En;
1083-
if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP))
1084-
res0 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);
1085-
if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, CMOW, IMP))
1086-
res0 |= HCRX_EL2_CMOW;
1087-
if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP))
1088-
res0 |= (HCRX_EL2_VFNMI | HCRX_EL2_VINMI | HCRX_EL2_TALLINT);
1089-
if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) ||
1090-
!(read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS))
1091-
res0 |= HCRX_EL2_SMPME;
1092-
if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
1093-
res0 |= (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS);
1094-
if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V))
1095-
res0 |= HCRX_EL2_EnASR;
1096-
if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64))
1097-
res0 |= HCRX_EL2_EnALS;
1098-
if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA))
1099-
res0 |= HCRX_EL2_EnAS0;
1061+
get_reg_fixed_bits(kvm, HCRX_EL2, &res0, &res1);
11001062
set_sysreg_masks(kvm, HCRX_EL2, res0, res1);
11011063

11021064
/* HFG[RW]TR_EL2 */

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