Skip to content

Commit 22513c0

Browse files
Marc Zyngieroupton
Marc Zyngier
authored and
oupton
committed
arm64: sysreg: Add layout for ICH_HCR_EL2
The ICH_HCR_EL2-related macros are missing a number of control bits that we are about to handle. Take this opportunity to fully describe the layout of that register as part of the automatic generation infrastructure. This results in a bit of churn, unfortunately. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250225172930.1850838-2-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
1 parent 0ad2507 commit 22513c0

File tree

7 files changed

+50
-51
lines changed

7 files changed

+50
-51
lines changed

‎arch/arm64/include/asm/sysreg.h

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,6 @@
562562

563563
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
564564
#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
565-
#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
566565
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
567566
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
568567
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
@@ -1003,17 +1002,6 @@
10031002
#define ICH_LR_PRIORITY_SHIFT 48
10041003
#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
10051004

1006-
/* ICH_HCR_EL2 bit definitions */
1007-
#define ICH_HCR_EN (1 << 0)
1008-
#define ICH_HCR_UIE (1 << 1)
1009-
#define ICH_HCR_NPIE (1 << 3)
1010-
#define ICH_HCR_TC (1 << 10)
1011-
#define ICH_HCR_TALL0 (1 << 11)
1012-
#define ICH_HCR_TALL1 (1 << 12)
1013-
#define ICH_HCR_TDIR (1 << 14)
1014-
#define ICH_HCR_EOIcount_SHIFT 27
1015-
#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
1016-
10171005
/* ICH_VMCR_EL2 bit definitions */
10181006
#define ICH_VMCR_ACK_CTL_SHIFT 2
10191007
#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)

‎arch/arm64/kvm/emulate-nested.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -412,26 +412,26 @@ static const struct trap_bits coarse_trap_bits[] = {
412412
},
413413
[CGT_ICH_HCR_TC] = {
414414
.index = ICH_HCR_EL2,
415-
.value = ICH_HCR_TC,
416-
.mask = ICH_HCR_TC,
415+
.value = ICH_HCR_EL2_TC,
416+
.mask = ICH_HCR_EL2_TC,
417417
.behaviour = BEHAVE_FORWARD_RW,
418418
},
419419
[CGT_ICH_HCR_TALL0] = {
420420
.index = ICH_HCR_EL2,
421-
.value = ICH_HCR_TALL0,
422-
.mask = ICH_HCR_TALL0,
421+
.value = ICH_HCR_EL2_TALL0,
422+
.mask = ICH_HCR_EL2_TALL0,
423423
.behaviour = BEHAVE_FORWARD_RW,
424424
},
425425
[CGT_ICH_HCR_TALL1] = {
426426
.index = ICH_HCR_EL2,
427-
.value = ICH_HCR_TALL1,
428-
.mask = ICH_HCR_TALL1,
427+
.value = ICH_HCR_EL2_TALL1,
428+
.mask = ICH_HCR_EL2_TALL1,
429429
.behaviour = BEHAVE_FORWARD_RW,
430430
},
431431
[CGT_ICH_HCR_TDIR] = {
432432
.index = ICH_HCR_EL2,
433-
.value = ICH_HCR_TDIR,
434-
.mask = ICH_HCR_TDIR,
433+
.value = ICH_HCR_EL2_TDIR,
434+
.mask = ICH_HCR_EL2_TDIR,
435435
.behaviour = BEHAVE_FORWARD_RW,
436436
},
437437
};

‎arch/arm64/kvm/hyp/vgic-v3-sr.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if)
218218

219219
elrsr = read_gicreg(ICH_ELRSR_EL2);
220220

221-
write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);
221+
write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EL2_En, ICH_HCR_EL2);
222222

223223
for (i = 0; i < used_lrs; i++) {
224224
if (elrsr & (1 << i))
@@ -274,7 +274,7 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if)
274274
* system registers to trap to EL1 (duh), force ICC_SRE_EL1.SRE to 1
275275
* so that the trap bits can take effect. Yes, we *loves* the GIC.
276276
*/
277-
if (!(cpu_if->vgic_hcr & ICH_HCR_EN)) {
277+
if (!(cpu_if->vgic_hcr & ICH_HCR_EL2_En)) {
278278
write_gicreg(ICC_SRE_EL1_SRE, ICC_SRE_EL1);
279279
isb();
280280
} else if (!cpu_if->vgic_sre) {
@@ -752,7 +752,7 @@ static void __vgic_v3_bump_eoicount(void)
752752
u32 hcr;
753753

754754
hcr = read_gicreg(ICH_HCR_EL2);
755-
hcr += 1 << ICH_HCR_EOIcount_SHIFT;
755+
hcr += 1 << ICH_HCR_EL2_EOIcount_SHIFT;
756756
write_gicreg(hcr, ICH_HCR_EL2);
757757
}
758758

@@ -1069,7 +1069,7 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu,
10691069
case SYS_ICC_EOIR0_EL1:
10701070
case SYS_ICC_HPPIR0_EL1:
10711071
case SYS_ICC_IAR0_EL1:
1072-
return ich_hcr & ICH_HCR_TALL0;
1072+
return ich_hcr & ICH_HCR_EL2_TALL0;
10731073

10741074
case SYS_ICC_IGRPEN1_EL1:
10751075
if (is_read &&
@@ -1090,18 +1090,18 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu,
10901090
case SYS_ICC_EOIR1_EL1:
10911091
case SYS_ICC_HPPIR1_EL1:
10921092
case SYS_ICC_IAR1_EL1:
1093-
return ich_hcr & ICH_HCR_TALL1;
1093+
return ich_hcr & ICH_HCR_EL2_TALL1;
10941094

10951095
case SYS_ICC_DIR_EL1:
1096-
if (ich_hcr & ICH_HCR_TDIR)
1096+
if (ich_hcr & ICH_HCR_EL2_TDIR)
10971097
return true;
10981098

10991099
fallthrough;
11001100

11011101
case SYS_ICC_RPR_EL1:
11021102
case SYS_ICC_CTLR_EL1:
11031103
case SYS_ICC_PMR_EL1:
1104-
return ich_hcr & ICH_HCR_TC;
1104+
return ich_hcr & ICH_HCR_EL2_TC;
11051105

11061106
default:
11071107
return false;

‎arch/arm64/kvm/vgic/vgic-v3.c

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
2424
{
2525
struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
2626

27-
cpuif->vgic_hcr |= ICH_HCR_UIE;
27+
cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;
2828
}
2929

3030
static bool lr_signals_eoi_mi(u64 lr_val)
@@ -42,7 +42,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
4242

4343
DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
4444

45-
cpuif->vgic_hcr &= ~ICH_HCR_UIE;
45+
cpuif->vgic_hcr &= ~ICH_HCR_EL2_UIE;
4646

4747
for (lr = 0; lr < cpuif->used_lrs; lr++) {
4848
u64 val = cpuif->vgic_lr[lr];
@@ -292,7 +292,7 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
292292
ICH_VTR_PRI_BITS_SHIFT) + 1;
293293

294294
/* Get the show on the road... */
295-
vgic_v3->vgic_hcr = ICH_HCR_EN;
295+
vgic_v3->vgic_hcr = ICH_HCR_EL2_En;
296296
}
297297

298298
void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
@@ -301,18 +301,19 @@ void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
301301

302302
/* Hide GICv3 sysreg if necessary */
303303
if (!kvm_has_gicv3(vcpu->kvm)) {
304-
vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC;
304+
vgic_v3->vgic_hcr |= (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |
305+
ICH_HCR_EL2_TC);
305306
return;
306307
}
307308

308309
if (group0_trap)
309-
vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
310+
vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL0;
310311
if (group1_trap)
311-
vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
312+
vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL1;
312313
if (common_trap)
313-
vgic_v3->vgic_hcr |= ICH_HCR_TC;
314+
vgic_v3->vgic_hcr |= ICH_HCR_EL2_TC;
314315
if (dir_trap)
315-
vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
316+
vgic_v3->vgic_hcr |= ICH_HCR_EL2_TDIR;
316317
}
317318

318319
int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)

‎arch/arm64/tools/sysreg

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3035,6 +3035,28 @@ Field 31:16 PhyPARTID29
30353035
Field 15:0 PhyPARTID28
30363036
EndSysreg
30373037

3038+
Sysreg ICH_HCR_EL2 3 4 12 11 0
3039+
Res0 63:32
3040+
Field 31:27 EOIcount
3041+
Res0 26:16
3042+
Field 15 DVIM
3043+
Field 14 TDIR
3044+
Field 13 TSEI
3045+
Field 12 TALL1
3046+
Field 11 TALL0
3047+
Field 10 TC
3048+
Res0 9
3049+
Field 8 vSGIEOICount
3050+
Field 7 VGrp1DIE
3051+
Field 6 VGrp1EIE
3052+
Field 5 VGrp0DIE
3053+
Field 4 VGrp0EIE
3054+
Field 3 NPIE
3055+
Field 2 LRENPIE
3056+
Field 1 UIE
3057+
Field 0 En
3058+
EndSysreg
3059+
30383060
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
30393061
Fields CONTEXTIDR_ELx
30403062
EndSysreg

‎drivers/irqchip/irq-apple-aic.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -409,15 +409,15 @@ static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
409409
* in use, and be cleared when coming back from the handler.
410410
*/
411411
if (is_kernel_in_hyp_mode() &&
412-
(read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&
412+
(read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
413413
read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {
414414
generic_handle_domain_irq(aic_irqc->hw_domain,
415415
AIC_FIQ_HWIRQ(AIC_VGIC_MI));
416416

417-
if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&
417+
if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
418418
read_sysreg_s(SYS_ICH_MISR_EL2))) {
419419
pr_err_ratelimited("vGIC IRQ fired and not handled by KVM, disabling.\n");
420-
sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);
420+
sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
421421
}
422422
}
423423
}
@@ -841,7 +841,7 @@ static int aic_init_cpu(unsigned int cpu)
841841
VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);
842842

843843
/* vGIC maintenance IRQ */
844-
sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);
844+
sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
845845
}
846846

847847
/* PMC FIQ */

‎tools/arch/arm64/include/asm/sysreg.h

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -558,7 +558,6 @@
558558

559559
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560560
#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
561-
#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
562561
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
563562
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
564563
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
@@ -999,17 +998,6 @@
999998
#define ICH_LR_PRIORITY_SHIFT 48
1000999
#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
10011000

1002-
/* ICH_HCR_EL2 bit definitions */
1003-
#define ICH_HCR_EN (1 << 0)
1004-
#define ICH_HCR_UIE (1 << 1)
1005-
#define ICH_HCR_NPIE (1 << 3)
1006-
#define ICH_HCR_TC (1 << 10)
1007-
#define ICH_HCR_TALL0 (1 << 11)
1008-
#define ICH_HCR_TALL1 (1 << 12)
1009-
#define ICH_HCR_TDIR (1 << 14)
1010-
#define ICH_HCR_EOIcount_SHIFT 27
1011-
#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
1012-
10131001
/* ICH_VMCR_EL2 bit definitions */
10141002
#define ICH_VMCR_ACK_CTL_SHIFT 2
10151003
#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)

0 commit comments

Comments
 (0)