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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | + |
| 3 | +#ifndef SELFTEST_KVM_PROCESSOR_H |
| 4 | +#define SELFTEST_KVM_PROCESSOR_H |
| 5 | + |
| 6 | +#ifndef __ASSEMBLER__ |
| 7 | +#include "ucall_common.h" |
| 8 | + |
| 9 | +#else |
| 10 | +/* general registers */ |
| 11 | +#define zero $r0 |
| 12 | +#define ra $r1 |
| 13 | +#define tp $r2 |
| 14 | +#define sp $r3 |
| 15 | +#define a0 $r4 |
| 16 | +#define a1 $r5 |
| 17 | +#define a2 $r6 |
| 18 | +#define a3 $r7 |
| 19 | +#define a4 $r8 |
| 20 | +#define a5 $r9 |
| 21 | +#define a6 $r10 |
| 22 | +#define a7 $r11 |
| 23 | +#define t0 $r12 |
| 24 | +#define t1 $r13 |
| 25 | +#define t2 $r14 |
| 26 | +#define t3 $r15 |
| 27 | +#define t4 $r16 |
| 28 | +#define t5 $r17 |
| 29 | +#define t6 $r18 |
| 30 | +#define t7 $r19 |
| 31 | +#define t8 $r20 |
| 32 | +#define u0 $r21 |
| 33 | +#define fp $r22 |
| 34 | +#define s0 $r23 |
| 35 | +#define s1 $r24 |
| 36 | +#define s2 $r25 |
| 37 | +#define s3 $r26 |
| 38 | +#define s4 $r27 |
| 39 | +#define s5 $r28 |
| 40 | +#define s6 $r29 |
| 41 | +#define s7 $r30 |
| 42 | +#define s8 $r31 |
| 43 | +#endif |
| 44 | + |
| 45 | +/* |
| 46 | + * LoongArch page table entry definition |
| 47 | + * Original header file arch/loongarch/include/asm/loongarch.h |
| 48 | + */ |
| 49 | +#define _PAGE_VALID_SHIFT 0 |
| 50 | +#define _PAGE_DIRTY_SHIFT 1 |
| 51 | +#define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */ |
| 52 | +#define PLV_KERN 0 |
| 53 | +#define PLV_USER 3 |
| 54 | +#define PLV_MASK 0x3 |
| 55 | +#define _CACHE_SHIFT 4 /* 4~5, two bits */ |
| 56 | +#define _PAGE_PRESENT_SHIFT 7 |
| 57 | +#define _PAGE_WRITE_SHIFT 8 |
| 58 | + |
| 59 | +#define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT) |
| 60 | +#define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT) |
| 61 | +#define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT) |
| 62 | +#define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT) |
| 63 | +#define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT) |
| 64 | +#define __READABLE (_PAGE_VALID) |
| 65 | +#define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE) |
| 66 | +/* Coherent Cached */ |
| 67 | +#define _CACHE_CC BIT_ULL(_CACHE_SHIFT) |
| 68 | +#define PS_4K 0x0000000c |
| 69 | +#define PS_16K 0x0000000e |
| 70 | +#define PS_64K 0x00000010 |
| 71 | +#define PS_DEFAULT_SIZE PS_16K |
| 72 | + |
| 73 | +/* LoongArch Basic CSR registers */ |
| 74 | +#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ |
| 75 | +#define CSR_CRMD_PG_SHIFT 4 |
| 76 | +#define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT) |
| 77 | +#define CSR_CRMD_IE_SHIFT 2 |
| 78 | +#define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT) |
| 79 | +#define CSR_CRMD_PLV_SHIFT 0 |
| 80 | +#define CSR_CRMD_PLV_WIDTH 2 |
| 81 | +#define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT) |
| 82 | +#define PLV_MASK 0x3 |
| 83 | +#define LOONGARCH_CSR_PRMD 0x1 |
| 84 | +#define LOONGARCH_CSR_EUEN 0x2 |
| 85 | +#define LOONGARCH_CSR_ECFG 0x4 |
| 86 | +#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ |
| 87 | +#define LOONGARCH_CSR_ERA 0x6 /* ERA */ |
| 88 | +#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ |
| 89 | +#define LOONGARCH_CSR_EENTRY 0xc |
| 90 | +#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */ |
| 91 | +#define CSR_TLBIDX_PS_SHIFT 24 |
| 92 | +#define CSR_TLBIDX_PS_WIDTH 6 |
| 93 | +#define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT) |
| 94 | +#define CSR_TLBIDX_SIZEM 0x3f000000 |
| 95 | +#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT |
| 96 | +#define LOONGARCH_CSR_ASID 0x18 /* ASID */ |
| 97 | +#define LOONGARCH_CSR_PGDL 0x19 |
| 98 | +#define LOONGARCH_CSR_PGDH 0x1a |
| 99 | +/* Page table base */ |
| 100 | +#define LOONGARCH_CSR_PGD 0x1b |
| 101 | +#define LOONGARCH_CSR_PWCTL0 0x1c |
| 102 | +#define LOONGARCH_CSR_PWCTL1 0x1d |
| 103 | +#define LOONGARCH_CSR_STLBPGSIZE 0x1e |
| 104 | +#define LOONGARCH_CSR_CPUID 0x20 |
| 105 | +#define LOONGARCH_CSR_KS0 0x30 |
| 106 | +#define LOONGARCH_CSR_KS1 0x31 |
| 107 | +#define LOONGARCH_CSR_TMID 0x40 |
| 108 | +#define LOONGARCH_CSR_TCFG 0x41 |
| 109 | +/* TLB refill exception entry */ |
| 110 | +#define LOONGARCH_CSR_TLBRENTRY 0x88 |
| 111 | +#define LOONGARCH_CSR_TLBRSAVE 0x8b |
| 112 | +#define LOONGARCH_CSR_TLBREHI 0x8e |
| 113 | +#define CSR_TLBREHI_PS_SHIFT 0 |
| 114 | +#define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT) |
| 115 | + |
| 116 | +#define EXREGS_GPRS (32) |
| 117 | + |
| 118 | +#ifndef __ASSEMBLER__ |
| 119 | +void handle_tlb_refill(void); |
| 120 | +void handle_exception(void); |
| 121 | + |
| 122 | +struct ex_regs { |
| 123 | + unsigned long regs[EXREGS_GPRS]; |
| 124 | + unsigned long pc; |
| 125 | + unsigned long estat; |
| 126 | + unsigned long badv; |
| 127 | +}; |
| 128 | + |
| 129 | +#define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc) |
| 130 | +#define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat) |
| 131 | +#define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv) |
| 132 | +#define EXREGS_SIZE sizeof(struct ex_regs) |
| 133 | + |
| 134 | +#else |
| 135 | +#define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8) |
| 136 | +#define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8) |
| 137 | +#define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8) |
| 138 | +#define EXREGS_SIZE ((EXREGS_GPRS + 3) * 8) |
| 139 | +#endif |
| 140 | + |
| 141 | +#endif /* SELFTEST_KVM_PROCESSOR_H */ |
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