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#include "sys_regs.h"
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- /* Protection against the sysreg repainting madness... */
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- #define NV_FTR (r , f ) ID_AA64##r##_EL1_##f
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-
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/*
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* Ratio of live shadow S2 MMU per vcpu. This is a trade-off between
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* memory usage and potential number of different sets of S2 PTs in
@@ -54,6 +51,10 @@ int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu)
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struct kvm_s2_mmu * tmp ;
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int num_mmus , ret = 0 ;
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+ if (test_bit (KVM_ARM_VCPU_HAS_EL2_E2H0 , kvm -> arch .vcpu_features ) &&
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+ !cpus_have_final_cap (ARM64_HAS_HCR_NV1 ))
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+ return - EINVAL ;
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+
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/*
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* Let's treat memory allocation failures as benign: If we fail to
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* allocate anything, return an error and keep the allocated array
@@ -807,134 +808,151 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
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* This list should get updated as new features get added to the NV
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* support, and new extension to the architecture.
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*/
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- static void limit_nv_id_regs (struct kvm * kvm )
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+ u64 limit_nv_id_reg (struct kvm * kvm , u32 reg , u64 val )
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{
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- u64 val , tmp ;
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-
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- /* Support everything but TME */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64ISAR0_EL1 );
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- val &= ~NV_FTR (ISAR0 , TME );
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64ISAR0_EL1 , val );
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-
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- /* Support everything but Spec Invalidation and LS64 */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64ISAR1_EL1 );
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- val &= ~(NV_FTR (ISAR1 , LS64 ) |
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- NV_FTR (ISAR1 , SPECRES ));
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64ISAR1_EL1 , val );
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-
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- /* No AMU, MPAM, S-EL2, or RAS */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64PFR0_EL1 );
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- val &= ~(GENMASK_ULL (55 , 52 ) |
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- NV_FTR (PFR0 , AMU ) |
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- NV_FTR (PFR0 , MPAM ) |
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- NV_FTR (PFR0 , SEL2 ) |
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- NV_FTR (PFR0 , RAS ) |
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- NV_FTR (PFR0 , EL3 ) |
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- NV_FTR (PFR0 , EL2 ) |
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- NV_FTR (PFR0 , EL1 ) |
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- NV_FTR (PFR0 , EL0 ));
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- /* 64bit only at any EL */
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- val |= FIELD_PREP (NV_FTR (PFR0 , EL0 ), 0b0001 );
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- val |= FIELD_PREP (NV_FTR (PFR0 , EL1 ), 0b0001 );
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- val |= FIELD_PREP (NV_FTR (PFR0 , EL2 ), 0b0001 );
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- val |= FIELD_PREP (NV_FTR (PFR0 , EL3 ), 0b0001 );
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64PFR0_EL1 , val );
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-
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- /* Only support BTI, SSBS, CSV2_frac */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64PFR1_EL1 );
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- val &= (NV_FTR (PFR1 , BT ) |
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- NV_FTR (PFR1 , SSBS ) |
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- NV_FTR (PFR1 , CSV2_frac ));
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64PFR1_EL1 , val );
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-
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- /* Hide ECV, ExS, Secure Memory */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64MMFR0_EL1 );
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- val &= ~(NV_FTR (MMFR0 , ECV ) |
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- NV_FTR (MMFR0 , EXS ) |
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- NV_FTR (MMFR0 , TGRAN4_2 ) |
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- NV_FTR (MMFR0 , TGRAN16_2 ) |
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- NV_FTR (MMFR0 , TGRAN64_2 ) |
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- NV_FTR (MMFR0 , SNSMEM ));
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-
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- /* Disallow unsupported S2 page sizes */
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- switch (PAGE_SIZE ) {
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- case SZ_64K :
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- val |= FIELD_PREP (NV_FTR (MMFR0 , TGRAN16_2 ), 0b0001 );
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- fallthrough ;
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- case SZ_16K :
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- val |= FIELD_PREP (NV_FTR (MMFR0 , TGRAN4_2 ), 0b0001 );
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- fallthrough ;
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- case SZ_4K :
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- /* Support everything */
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+ switch (reg ) {
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+ case SYS_ID_AA64ISAR0_EL1 :
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+ /* Support everything but TME */
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+ val &= ~ID_AA64ISAR0_EL1_TME ;
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break ;
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- }
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- /*
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- * Since we can't support a guest S2 page size smaller than
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- * the host's own page size (due to KVM only populating its
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- * own S2 using the kernel's page size), advertise the
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- * limitation using FEAT_GTG.
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- */
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- switch (PAGE_SIZE ) {
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- case SZ_4K :
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- val |= FIELD_PREP (NV_FTR (MMFR0 , TGRAN4_2 ), 0b0010 );
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- fallthrough ;
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- case SZ_16K :
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- val |= FIELD_PREP (NV_FTR (MMFR0 , TGRAN16_2 ), 0b0010 );
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- fallthrough ;
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- case SZ_64K :
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- val |= FIELD_PREP (NV_FTR (MMFR0 , TGRAN64_2 ), 0b0010 );
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+
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+ case SYS_ID_AA64ISAR1_EL1 :
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+ /* Support everything but LS64 and Spec Invalidation */
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+ val &= ~(ID_AA64ISAR1_EL1_LS64 |
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+ ID_AA64ISAR1_EL1_SPECRES );
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+ break ;
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+
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+ case SYS_ID_AA64PFR0_EL1 :
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+ /* No RME, AMU, MPAM, S-EL2, or RAS */
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+ val &= ~(ID_AA64PFR0_EL1_RME |
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+ ID_AA64PFR0_EL1_AMU |
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+ ID_AA64PFR0_EL1_MPAM |
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+ ID_AA64PFR0_EL1_SEL2 |
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+ ID_AA64PFR0_EL1_RAS |
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+ ID_AA64PFR0_EL1_EL3 |
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+ ID_AA64PFR0_EL1_EL2 |
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+ ID_AA64PFR0_EL1_EL1 |
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+ ID_AA64PFR0_EL1_EL0 );
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+ /* 64bit only at any EL */
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64PFR0_EL1 , EL0 , IMP );
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64PFR0_EL1 , EL1 , IMP );
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64PFR0_EL1 , EL2 , IMP );
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64PFR0_EL1 , EL3 , IMP );
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+ break ;
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+
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+ case SYS_ID_AA64PFR1_EL1 :
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+ /* Only support BTI, SSBS, CSV2_frac */
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+ val &= (ID_AA64PFR1_EL1_BT |
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+ ID_AA64PFR1_EL1_SSBS |
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+ ID_AA64PFR1_EL1_CSV2_frac );
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+ break ;
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+
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+ case SYS_ID_AA64MMFR0_EL1 :
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+ /* Hide ExS, Secure Memory */
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+ val &= ~(ID_AA64MMFR0_EL1_EXS |
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+ ID_AA64MMFR0_EL1_TGRAN4_2 |
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+ ID_AA64MMFR0_EL1_TGRAN16_2 |
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+ ID_AA64MMFR0_EL1_TGRAN64_2 |
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+ ID_AA64MMFR0_EL1_SNSMEM );
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+
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+ /* Hide CNTPOFF if present */
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+ val = ID_REG_LIMIT_FIELD_ENUM (val , ID_AA64MMFR0_EL1 , ECV , IMP );
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+
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+ /* Disallow unsupported S2 page sizes */
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+ switch (PAGE_SIZE ) {
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+ case SZ_64K :
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR0_EL1 , TGRAN16_2 , NI );
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+ fallthrough ;
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+ case SZ_16K :
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR0_EL1 , TGRAN4_2 , NI );
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+ fallthrough ;
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+ case SZ_4K :
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+ /* Support everything */
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+ break ;
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+ }
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+
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+ /*
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+ * Since we can't support a guest S2 page size smaller
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+ * than the host's own page size (due to KVM only
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+ * populating its own S2 using the kernel's page
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+ * size), advertise the limitation using FEAT_GTG.
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+ */
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+ switch (PAGE_SIZE ) {
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+ case SZ_4K :
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR0_EL1 , TGRAN4_2 , IMP );
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+ fallthrough ;
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+ case SZ_16K :
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR0_EL1 , TGRAN16_2 , IMP );
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+ fallthrough ;
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+ case SZ_64K :
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR0_EL1 , TGRAN64_2 , IMP );
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+ break ;
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+ }
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+
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+ /* Cap PARange to 48bits */
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+ val = ID_REG_LIMIT_FIELD_ENUM (val , ID_AA64MMFR0_EL1 , PARANGE , 48 );
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+ break ;
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+
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+ case SYS_ID_AA64MMFR1_EL1 :
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+ val &= (ID_AA64MMFR1_EL1_HCX |
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+ ID_AA64MMFR1_EL1_PAN |
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+ ID_AA64MMFR1_EL1_LO |
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+ ID_AA64MMFR1_EL1_HPDS |
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+ ID_AA64MMFR1_EL1_VH |
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+ ID_AA64MMFR1_EL1_VMIDBits );
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+ /* FEAT_E2H0 implies no VHE */
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+ if (test_bit (KVM_ARM_VCPU_HAS_EL2_E2H0 , kvm -> arch .vcpu_features ))
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+ val &= ~ID_AA64MMFR1_EL1_VH ;
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+ break ;
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+
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+ case SYS_ID_AA64MMFR2_EL1 :
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+ val &= ~(ID_AA64MMFR2_EL1_BBM |
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+ ID_AA64MMFR2_EL1_TTL |
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+ GENMASK_ULL (47 , 44 ) |
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+ ID_AA64MMFR2_EL1_ST |
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+ ID_AA64MMFR2_EL1_CCIDX |
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+ ID_AA64MMFR2_EL1_VARange );
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+
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+ /* Force TTL support */
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR2_EL1 , TTL , IMP );
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+ break ;
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+
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+ case SYS_ID_AA64MMFR4_EL1 :
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+ /*
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+ * You get EITHER
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+ *
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+ * - FEAT_VHE without FEAT_E2H0
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+ * - FEAT_NV limited to FEAT_NV2
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+ * - HCR_EL2.NV1 being RES0
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+ *
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+ * OR
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+ *
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+ * - FEAT_E2H0 without FEAT_VHE nor FEAT_NV
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+ *
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+ * Life is too short for anything else.
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+ */
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+ if (test_bit (KVM_ARM_VCPU_HAS_EL2_E2H0 , kvm -> arch .vcpu_features )) {
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+ val = 0 ;
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+ } else {
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+ val = SYS_FIELD_PREP_ENUM (ID_AA64MMFR4_EL1 , NV_frac , NV2_ONLY );
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+ val |= SYS_FIELD_PREP_ENUM (ID_AA64MMFR4_EL1 , E2H0 , NI_NV1 );
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+ }
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+ break ;
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+
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+ case SYS_ID_AA64DFR0_EL1 :
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+ /* Only limited support for PMU, Debug, BPs, WPs, and HPMN0 */
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+ val &= (ID_AA64DFR0_EL1_PMUVer |
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+ ID_AA64DFR0_EL1_WRPs |
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+ ID_AA64DFR0_EL1_BRPs |
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+ ID_AA64DFR0_EL1_DebugVer |
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+ ID_AA64DFR0_EL1_HPMN0 );
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+
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+ /* Cap Debug to ARMv8.1 */
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+ val = ID_REG_LIMIT_FIELD_ENUM (val , ID_AA64DFR0_EL1 , DebugVer , VHE );
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break ;
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}
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- /* Cap PARange to 48bits */
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- tmp = FIELD_GET (NV_FTR (MMFR0 , PARANGE ), val );
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- if (tmp > 0b0101 ) {
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- val &= ~NV_FTR (MMFR0 , PARANGE );
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- val |= FIELD_PREP (NV_FTR (MMFR0 , PARANGE ), 0b0101 );
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- }
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64MMFR0_EL1 , val );
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-
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64MMFR1_EL1 );
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- val &= (NV_FTR (MMFR1 , HCX ) |
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- NV_FTR (MMFR1 , PAN ) |
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- NV_FTR (MMFR1 , LO ) |
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- NV_FTR (MMFR1 , HPDS ) |
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- NV_FTR (MMFR1 , VH ) |
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- NV_FTR (MMFR1 , VMIDBits ));
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64MMFR1_EL1 , val );
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-
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64MMFR2_EL1 );
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- val &= ~(NV_FTR (MMFR2 , BBM ) |
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- NV_FTR (MMFR2 , TTL ) |
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- GENMASK_ULL (47 , 44 ) |
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- NV_FTR (MMFR2 , ST ) |
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- NV_FTR (MMFR2 , CCIDX ) |
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- NV_FTR (MMFR2 , VARange ));
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-
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- /* Force TTL support */
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- val |= FIELD_PREP (NV_FTR (MMFR2 , TTL ), 0b0001 );
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64MMFR2_EL1 , val );
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-
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- val = 0 ;
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- if (!cpus_have_final_cap (ARM64_HAS_HCR_NV1 ))
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- val |= FIELD_PREP (NV_FTR (MMFR4 , E2H0 ),
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- ID_AA64MMFR4_EL1_E2H0_NI_NV1 );
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64MMFR4_EL1 , val );
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-
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- /* Only limited support for PMU, Debug, BPs, WPs, and HPMN0 */
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- val = kvm_read_vm_id_reg (kvm , SYS_ID_AA64DFR0_EL1 );
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- val &= (NV_FTR (DFR0 , PMUVer ) |
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- NV_FTR (DFR0 , WRPs ) |
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- NV_FTR (DFR0 , BRPs ) |
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- NV_FTR (DFR0 , DebugVer ) |
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- NV_FTR (DFR0 , HPMN0 ));
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-
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- /* Cap Debug to ARMv8.1 */
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- tmp = FIELD_GET (NV_FTR (DFR0 , DebugVer ), val );
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- if (tmp > 0b0111 ) {
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- val &= ~NV_FTR (DFR0 , DebugVer );
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- val |= FIELD_PREP (NV_FTR (DFR0 , DebugVer ), 0b0111 );
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- }
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- kvm_set_vm_id_reg (kvm , SYS_ID_AA64DFR0_EL1 , val );
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+
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+ return val ;
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}
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u64 kvm_vcpu_apply_reg_masks (const struct kvm_vcpu * vcpu ,
@@ -981,8 +999,6 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
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if (!kvm -> arch .sysreg_masks )
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return - ENOMEM ;
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- limit_nv_id_regs (kvm );
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-
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/* VTTBR_EL2 */
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res0 = res1 = 0 ;
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if (!kvm_has_feat_enum (kvm , ID_AA64MMFR1_EL1 , VMIDBits , 16 ))
@@ -1021,10 +1037,11 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
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res0 |= HCR_FIEN ;
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if (!kvm_has_feat (kvm , ID_AA64MMFR2_EL1 , FWB , IMP ))
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res0 |= HCR_FWB ;
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- if (!kvm_has_feat (kvm , ID_AA64MMFR2_EL1 , NV , NV2 ))
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- res0 |= HCR_NV2 ;
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- if (!kvm_has_feat (kvm , ID_AA64MMFR2_EL1 , NV , IMP ))
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- res0 |= (HCR_AT | HCR_NV1 | HCR_NV );
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+ /* Implementation choice: NV2 is the only supported config */
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+ if (!kvm_has_feat (kvm , ID_AA64MMFR4_EL1 , NV_frac , NV2_ONLY ))
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+ res0 |= (HCR_NV2 | HCR_NV | HCR_AT );
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+ if (!kvm_has_feat (kvm , ID_AA64MMFR4_EL1 , E2H0 , NI ))
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+ res0 |= HCR_NV1 ;
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if (!(kvm_vcpu_has_feature (kvm , KVM_ARM_VCPU_PTRAUTH_ADDRESS ) &&
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kvm_vcpu_has_feature (kvm , KVM_ARM_VCPU_PTRAUTH_GENERIC )))
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res0 |= (HCR_API | HCR_APK );
@@ -1034,6 +1051,8 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
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res0 |= (HCR_TEA | HCR_TERR );
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if (!kvm_has_feat (kvm , ID_AA64MMFR1_EL1 , LO , IMP ))
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res0 |= HCR_TLOR ;
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+ if (!kvm_has_feat (kvm , ID_AA64MMFR1_EL1 , VH , IMP ))
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+ res0 |= HCR_E2H ;
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if (!kvm_has_feat (kvm , ID_AA64MMFR4_EL1 , E2H0 , IMP ))
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res1 |= HCR_E2H ;
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set_sysreg_masks (kvm , HCR_EL2 , res0 , res1 );
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