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[RISCV] Handle LHS == 0 in isVLKnownLE (llvm#148860)
If a VL is zero then it's known to be less than or equal to every other VL. This looks weird on its own since a VL of zero isn't that common. The test diffs come from a type being split resulting in a VP intrinsic's EVL being zero. The motivation for this is to split off part of an upcoming patch I plan on submitting for RISCVVLOptimizer, which generalizes it to handle recurrences, and needs to reason about an initial state of demanded VLs set to zero.
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llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4812,6 +4812,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
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return true;
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if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel)
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return true;
4815+
if (LHS.isImm() && LHS.getImm() == 0)
4816+
return true;
48154817
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
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return false;
48174819
if (!LHS.isImm() || !RHS.isImm())

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -439,9 +439,10 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
439439
define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
440440
; CHECK-LABEL: vsadd_vi_v258i8_evl128:
441441
; CHECK: # %bb.0:
442-
; CHECK-NEXT: li a1, 128
443-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
442+
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
444443
; CHECK-NEXT: vlm.v v24, (a0)
444+
; CHECK-NEXT: li a0, 128
445+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
445446
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
446447
; CHECK-NEXT: vmv1r.v v0, v24
447448
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -435,9 +435,10 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
435435
define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
436436
; CHECK-LABEL: vsaddu_vi_v258i8_evl128:
437437
; CHECK: # %bb.0:
438-
; CHECK-NEXT: li a1, 128
439-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
438+
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
440439
; CHECK-NEXT: vlm.v v24, (a0)
440+
; CHECK-NEXT: li a0, 128
441+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
441442
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
442443
; CHECK-NEXT: vmv1r.v v0, v24
443444
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -454,14 +454,15 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
454454
define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
455455
; CHECK-LABEL: vssub_vi_v258i8_evl128:
456456
; CHECK: # %bb.0:
457-
; CHECK-NEXT: li a1, 128
458-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
457+
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
459458
; CHECK-NEXT: vlm.v v24, (a0)
460-
; CHECK-NEXT: li a0, -1
461-
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
459+
; CHECK-NEXT: li a0, 128
460+
; CHECK-NEXT: li a1, -1
461+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
462+
; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
462463
; CHECK-NEXT: vmv1r.v v0, v24
463464
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
464-
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
465+
; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
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; CHECK-NEXT: ret
466467
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
467468
ret <256 x i8> %v

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -449,14 +449,15 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
449449
define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
450450
; CHECK-LABEL: vssubu_vi_v258i8_evl128:
451451
; CHECK: # %bb.0:
452-
; CHECK-NEXT: li a1, 128
453-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
452+
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
454453
; CHECK-NEXT: vlm.v v24, (a0)
455-
; CHECK-NEXT: li a0, -1
456-
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
454+
; CHECK-NEXT: li a0, 128
455+
; CHECK-NEXT: li a1, -1
456+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
457+
; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
457458
; CHECK-NEXT: vmv1r.v v0, v24
458459
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
459-
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
460+
; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
460461
; CHECK-NEXT: ret
461462
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
462463
ret <256 x i8> %v

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