Request for Hardware Code Implementation Details #4
Description
Hi there!
I'm really impressed by your work on "8-bit Transformer Inference and Fine-tuning for Edge Accelerators" and have been exploring the quantized-training repository you provided. It's quite insightful and has been extremely helpful for my research.
However, I'm currently looking into the hardware implementation aspects of your research, particularly the RTL (Verilog/VHDL) code or hardware description for the posit and FP8 accelerators, which I understand is a crucial part of the work. I was wondering if you could share the hardware code or provide some guidance on where I might find it.
I'm interested in understanding how the hardware components, such as the MAC unit, encoder, decoder, and vector unit, are implemented and optimized for Posit8 and FP8. This would be incredibly valuable for my own projects and research.
Could you please let me know if the hardware code is available for sharing or if there are any plans to release it in the future? If there are any specific conditions or details I should be aware of regarding accessing this code, please don't hesitate to let me know.
Thank you so much for your time and consideration. I'm looking forward to your response.
Best regards,
JF