|
1 |
| -[{'normal/op_2_0': 'avg_pool_3x3', |
2 |
| -'normal/input_2_0': [1], |
3 |
| -'normal/op_2_1': 'avg_pool_3x3', |
4 |
| -'normal/input_2_1': [0], |
5 |
| -'normal/op_3_0': 'dil_conv_5x5', |
6 |
| -'normal/input_3_0': [0], |
7 |
| -'normal/op_3_1': 'max_pool_3x3', |
8 |
| -'normal/input_3_1': [2], |
9 |
| -'normal/op_4_0': 'dil_conv_3x3', |
10 |
| -'normal/input_4_0': [2], |
11 |
| -'normal/op_4_1': 'dil_conv_5x5', |
12 |
| -'normal/input_4_1': [0], |
13 |
| -'normal/op_5_0': 'dil_conv_3x3', |
14 |
| -'normal/input_5_0': [4], |
15 |
| -'normal/op_5_1': 'dil_conv_5x5', |
16 |
| -'normal/input_5_1': [3], |
17 |
| -'reduce/op_2_0': 'sep_conv_5x5', |
18 |
| -'reduce/input_2_0': [1], |
19 |
| -'reduce/op_2_1': 'dil_conv_5x5', |
20 |
| -'reduce/input_2_1': [0], |
21 |
| -'reduce/op_3_0': 'sep_conv_3x3', |
22 |
| -'reduce/input_3_0': [2], |
23 |
| -'reduce/op_3_1': 'sep_conv_3x3', |
24 |
| -'reduce/input_3_1': [1], |
25 |
| -'reduce/op_4_0': 'sep_conv_3x3', |
26 |
| -'reduce/input_4_0': [2], |
27 |
| -'reduce/op_4_1': 'sep_conv_3x3', |
28 |
| -'reduce/input_4_1': [1], |
29 |
| -'reduce/op_5_0': 'sep_conv_5x5', |
30 |
| -'reduce/input_5_0': [0], |
31 |
| -'reduce/op_5_1': 'sep_conv_5x5', |
32 |
| -'reduce/input_5_1': [3]}, |
33 |
| -{'normal/op_2_0': 'dil_conv_5x5', |
34 |
| -'normal/input_2_0': [0], |
35 |
| -'normal/op_2_1': 'dil_conv_3x3', |
36 |
| -'normal/input_2_1': [1], |
37 |
| -'normal/op_3_0': 'dil_conv_3x3', |
38 |
| -'normal/input_3_0': [0], |
39 |
| -'normal/op_3_1': 'max_pool_3x3', |
40 |
| -'normal/input_3_1': [1], |
41 |
| -'normal/op_4_0': 'max_pool_3x3', |
42 |
| -'normal/input_4_0': [2], |
43 |
| -'normal/op_4_1': 'dil_conv_5x5', |
44 |
| -'normal/input_4_1': [3], |
45 |
| -'normal/op_5_0': 'dil_conv_5x5', |
46 |
| -'normal/input_5_0': [2], |
47 |
| -'normal/op_5_1': 'sep_conv_5x5', |
48 |
| -'normal/input_5_1': [0], |
49 |
| -'reduce/op_2_0': 'skip_connect', |
50 |
| -'reduce/input_2_0': [1], |
51 |
| -'reduce/op_2_1': 'sep_conv_5x5', |
52 |
| -'reduce/input_2_1': [0], |
53 |
| -'reduce/op_3_0': 'sep_conv_5x5', |
54 |
| -'reduce/input_3_0': [0], |
55 |
| -'reduce/op_3_1': 'dil_conv_3x3', |
56 |
| -'reduce/input_3_1': [1], |
57 |
| -'reduce/op_4_0': 'skip_connect', |
58 |
| -'reduce/input_4_0': [2], |
59 |
| -'reduce/op_4_1': 'sep_conv_5x5', |
60 |
| -'reduce/input_4_1': [0], |
61 |
| -'reduce/op_5_0': 'skip_connect', |
62 |
| -'reduce/input_5_0': [1], |
63 |
| -'reduce/op_5_1': 'avg_pool_3x3', |
64 |
| -'reduce/input_5_1': [4]}, |
65 |
| -... |
66 |
| -] |
| 1 | +normal/op_2_0: avg_pool_3x3 |
| 2 | +normal/input_2_0: [0] |
| 3 | +normal/op_2_1: dil_conv_3x3 |
| 4 | +normal/input_2_1: [1] |
| 5 | +normal/op_3_0: sep_conv_3x3 |
| 6 | +normal/input_3_0: [2] |
| 7 | +normal/op_3_1: sep_conv_3x3 |
| 8 | +normal/input_3_1: [0] |
| 9 | +normal/op_4_0: dil_conv_3x3 |
| 10 | +normal/input_4_0: [3] |
| 11 | +normal/op_4_1: sep_conv_5x5 |
| 12 | +normal/input_4_1: [1] |
| 13 | +normal/op_5_0: dil_conv_3x3 |
| 14 | +normal/input_5_0: [0] |
| 15 | +normal/op_5_1: sep_conv_3x3 |
| 16 | +normal/input_5_1: [1] |
| 17 | +reduce/op_2_0: skip_connect |
| 18 | +reduce/input_2_0: [0] |
| 19 | +reduce/op_2_1: max_pool_3x3 |
| 20 | +reduce/input_2_1: [1] |
| 21 | +reduce/op_3_0: dil_conv_5x5 |
| 22 | +reduce/input_3_0: [1] |
| 23 | +reduce/op_3_1: sep_conv_3x3 |
| 24 | +reduce/input_3_1: [0] |
| 25 | +reduce/op_4_0: avg_pool_3x3 |
| 26 | +reduce/input_4_0: [1] |
| 27 | +reduce/op_4_1: dil_conv_5x5 |
| 28 | +reduce/input_4_1: [0] |
| 29 | +reduce/op_5_0: skip_connect |
| 30 | +reduce/input_5_0: [4] |
| 31 | +reduce/op_5_1: sep_conv_3x3 |
| 32 | +reduce/input_5_1: [3] |
| 33 | + |
| 34 | +normal/op_2_0: sep_conv_5x5 |
| 35 | +normal/input_2_0: [1] |
| 36 | +normal/op_2_1: sep_conv_5x5 |
| 37 | +normal/input_2_1: [0] |
| 38 | +normal/op_3_0: avg_pool_3x3 |
| 39 | +normal/input_3_0: [1] |
| 40 | +normal/op_3_1: sep_conv_3x3 |
| 41 | +normal/input_3_1: [0] |
| 42 | +normal/op_4_0: sep_conv_3x3 |
| 43 | +normal/input_4_0: [0] |
| 44 | +normal/op_4_1: avg_pool_3x3 |
| 45 | +normal/input_4_1: [1] |
| 46 | +normal/op_5_0: dil_conv_3x3 |
| 47 | +normal/input_5_0: [4] |
| 48 | +normal/op_5_1: sep_conv_3x3 |
| 49 | +normal/input_5_1: [2] |
| 50 | +reduce/op_2_0: sep_conv_3x3 |
| 51 | +reduce/input_2_0: [1] |
| 52 | +reduce/op_2_1: avg_pool_3x3 |
| 53 | +reduce/input_2_1: [0] |
| 54 | +reduce/op_3_0: max_pool_3x3 |
| 55 | +reduce/input_3_0: [1] |
| 56 | +reduce/op_3_1: sep_conv_5x5 |
| 57 | +reduce/input_3_1: [2] |
| 58 | +reduce/op_4_0: dil_conv_5x5 |
| 59 | +reduce/input_4_0: [3] |
| 60 | +reduce/op_4_1: avg_pool_3x3 |
| 61 | +reduce/input_4_1: [0] |
| 62 | +reduce/op_5_0: max_pool_3x3 |
| 63 | +reduce/input_5_0: [3] |
| 64 | +reduce/op_5_1: sep_conv_5x5 |
| 65 | +reduce/input_5_1: [2] |
| 66 | + |
| 67 | +normal/op_2_0: dil_conv_3x3 |
| 68 | +normal/input_2_0: [0] |
| 69 | +normal/op_2_1: dil_conv_5x5 |
| 70 | +normal/input_2_1: [1] |
| 71 | +normal/op_3_0: max_pool_3x3 |
| 72 | +normal/input_3_0: [0] |
| 73 | +normal/op_3_1: avg_pool_3x3 |
| 74 | +normal/input_3_1: [1] |
| 75 | +normal/op_4_0: sep_conv_5x5 |
| 76 | +normal/input_4_0: [2] |
| 77 | +normal/op_4_1: sep_conv_5x5 |
| 78 | +normal/input_4_1: [3] |
| 79 | +normal/op_5_0: max_pool_3x3 |
| 80 | +normal/input_5_0: [0] |
| 81 | +normal/op_5_1: max_pool_3x3 |
| 82 | +normal/input_5_1: [1] |
| 83 | +reduce/op_2_0: skip_connect |
| 84 | +reduce/input_2_0: [0] |
| 85 | +reduce/op_2_1: max_pool_3x3 |
| 86 | +reduce/input_2_1: [1] |
| 87 | +reduce/op_3_0: sep_conv_3x3 |
| 88 | +reduce/input_3_0: [2] |
| 89 | +reduce/op_3_1: dil_conv_5x5 |
| 90 | +reduce/input_3_1: [0] |
| 91 | +reduce/op_4_0: avg_pool_3x3 |
| 92 | +reduce/input_4_0: [3] |
| 93 | +reduce/op_4_1: avg_pool_3x3 |
| 94 | +reduce/input_4_1: [1] |
| 95 | +reduce/op_5_0: dil_conv_3x3 |
| 96 | +reduce/input_5_0: [0] |
| 97 | +reduce/op_5_1: dil_conv_3x3 |
| 98 | +reduce/input_5_1: [1] |
| 99 | + |
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