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| 1 | +normal/op_2_0: sep_conv_5x5 |
| 2 | +normal/input_2_0: [0] |
| 3 | +normal/op_2_1: max_pool_3x3 |
| 4 | +normal/input_2_1: [1] |
| 5 | +normal/op_3_0: avg_pool_3x3 |
| 6 | +normal/input_3_0: [1] |
| 7 | +normal/op_3_1: dil_conv_5x5 |
| 8 | +normal/input_3_1: [2] |
| 9 | +normal/op_4_0: skip_connect |
| 10 | +normal/input_4_0: [0] |
| 11 | +normal/op_4_1: skip_connect |
| 12 | +normal/input_4_1: [3] |
| 13 | +normal/op_5_0: max_pool_3x3 |
| 14 | +normal/input_5_0: [4] |
| 15 | +normal/op_5_1: skip_connect |
| 16 | +normal/input_5_1: [2] |
| 17 | +reduce/op_2_0: sep_conv_3x3 |
| 18 | +reduce/input_2_0: [0] |
| 19 | +reduce/op_2_1: sep_conv_3x3 |
| 20 | +reduce/input_2_1: [1] |
| 21 | +reduce/op_3_0: dil_conv_5x5 |
| 22 | +reduce/input_3_0: [0] |
| 23 | +reduce/op_3_1: sep_conv_3x3 |
| 24 | +reduce/input_3_1: [2] |
| 25 | +reduce/op_4_0: sep_conv_5x5 |
| 26 | +reduce/input_4_0: [2] |
| 27 | +reduce/op_4_1: sep_conv_3x3 |
| 28 | +reduce/input_4_1: [3] |
| 29 | +reduce/op_5_0: dil_conv_3x3 |
| 30 | +reduce/input_5_0: [2] |
| 31 | +reduce/op_5_1: sep_conv_3x3 |
| 32 | +reduce/input_5_1: [4] |
| 33 | + |
| 34 | +normal/op_2_0: dil_conv_3x3 |
| 35 | +normal/input_2_0: [0] |
| 36 | +normal/op_2_1: max_pool_3x3 |
| 37 | +normal/input_2_1: [1] |
| 38 | +normal/op_3_0: max_pool_3x3 |
| 39 | +normal/input_3_0: [0] |
| 40 | +normal/op_3_1: skip_connect |
| 41 | +normal/input_3_1: [2] |
| 42 | +normal/op_4_0: dil_conv_3x3 |
| 43 | +normal/input_4_0: [0] |
| 44 | +normal/op_4_1: dil_conv_3x3 |
| 45 | +normal/input_4_1: [1] |
| 46 | +normal/op_5_0: avg_pool_3x3 |
| 47 | +normal/input_5_0: [0] |
| 48 | +normal/op_5_1: avg_pool_3x3 |
| 49 | +normal/input_5_1: [1] |
| 50 | +reduce/op_2_0: sep_conv_3x3 |
| 51 | +reduce/input_2_0: [0] |
| 52 | +reduce/op_2_1: skip_connect |
| 53 | +reduce/input_2_1: [1] |
| 54 | +reduce/op_3_0: max_pool_3x3 |
| 55 | +reduce/input_3_0: [0] |
| 56 | +reduce/op_3_1: skip_connect |
| 57 | +reduce/input_3_1: [1] |
| 58 | +reduce/op_4_0: avg_pool_3x3 |
| 59 | +reduce/input_4_0: [1] |
| 60 | +reduce/op_4_1: max_pool_3x3 |
| 61 | +reduce/input_4_1: [0] |
| 62 | +reduce/op_5_0: max_pool_3x3 |
| 63 | +reduce/input_5_0: [1] |
| 64 | +reduce/op_5_1: avg_pool_3x3 |
| 65 | +reduce/input_5_1: [3] |
| 66 | + |
| 67 | +normal/op_2_0: max_pool_3x3 |
| 68 | +normal/input_2_0: [1] |
| 69 | +normal/op_2_1: dil_conv_3x3 |
| 70 | +normal/input_2_1: [0] |
| 71 | +normal/op_3_0: sep_conv_3x3 |
| 72 | +normal/input_3_0: [1] |
| 73 | +normal/op_3_1: max_pool_3x3 |
| 74 | +normal/input_3_1: [2] |
| 75 | +normal/op_4_0: max_pool_3x3 |
| 76 | +normal/input_4_0: [0] |
| 77 | +normal/op_4_1: sep_conv_3x3 |
| 78 | +normal/input_4_1: [2] |
| 79 | +normal/op_5_0: sep_conv_3x3 |
| 80 | +normal/input_5_0: [3] |
| 81 | +normal/op_5_1: skip_connect |
| 82 | +normal/input_5_1: [4] |
| 83 | +reduce/op_2_0: dil_conv_5x5 |
| 84 | +reduce/input_2_0: [1] |
| 85 | +reduce/op_2_1: sep_conv_5x5 |
| 86 | +reduce/input_2_1: [0] |
| 87 | +reduce/op_3_0: sep_conv_3x3 |
| 88 | +reduce/input_3_0: [1] |
| 89 | +reduce/op_3_1: max_pool_3x3 |
| 90 | +reduce/input_3_1: [0] |
| 91 | +reduce/op_4_0: dil_conv_5x5 |
| 92 | +reduce/input_4_0: [0] |
| 93 | +reduce/op_4_1: sep_conv_3x3 |
| 94 | +reduce/input_4_1: [1] |
| 95 | +reduce/op_5_0: sep_conv_5x5 |
| 96 | +reduce/input_5_0: [2] |
| 97 | +reduce/op_5_1: sep_conv_5x5 |
| 98 | +reduce/input_5_1: [0] |
| 99 | + |
| 100 | +normal/op_2_0: skip_connect |
| 101 | +normal/input_2_0: [1] |
| 102 | +normal/op_2_1: avg_pool_3x3 |
| 103 | +normal/input_2_1: [0] |
| 104 | +normal/op_3_0: sep_conv_3x3 |
| 105 | +normal/input_3_0: [2] |
| 106 | +normal/op_3_1: avg_pool_3x3 |
| 107 | +normal/input_3_1: [1] |
| 108 | +normal/op_4_0: max_pool_3x3 |
| 109 | +normal/input_4_0: [0] |
| 110 | +normal/op_4_1: skip_connect |
| 111 | +normal/input_4_1: [3] |
| 112 | +normal/op_5_0: sep_conv_5x5 |
| 113 | +normal/input_5_0: [1] |
| 114 | +normal/op_5_1: max_pool_3x3 |
| 115 | +normal/input_5_1: [4] |
| 116 | +reduce/op_2_0: dil_conv_3x3 |
| 117 | +reduce/input_2_0: [0] |
| 118 | +reduce/op_2_1: dil_conv_5x5 |
| 119 | +reduce/input_2_1: [1] |
| 120 | +reduce/op_3_0: sep_conv_3x3 |
| 121 | +reduce/input_3_0: [2] |
| 122 | +reduce/op_3_1: dil_conv_5x5 |
| 123 | +reduce/input_3_1: [1] |
| 124 | +reduce/op_4_0: dil_conv_5x5 |
| 125 | +reduce/input_4_0: [1] |
| 126 | +reduce/op_4_1: dil_conv_3x3 |
| 127 | +reduce/input_4_1: [2] |
| 128 | +reduce/op_5_0: dil_conv_5x5 |
| 129 | +reduce/input_5_0: [3] |
| 130 | +reduce/op_5_1: max_pool_3x3 |
| 131 | +reduce/input_5_1: [4] |
| 132 | + |
| 133 | +normal/op_2_0: dil_conv_5x5 |
| 134 | +normal/input_2_0: [1] |
| 135 | +normal/op_2_1: avg_pool_3x3 |
| 136 | +normal/input_2_1: [0] |
| 137 | +normal/op_3_0: skip_connect |
| 138 | +normal/input_3_0: [2] |
| 139 | +normal/op_3_1: avg_pool_3x3 |
| 140 | +normal/input_3_1: [0] |
| 141 | +normal/op_4_0: dil_conv_5x5 |
| 142 | +normal/input_4_0: [0] |
| 143 | +normal/op_4_1: dil_conv_3x3 |
| 144 | +normal/input_4_1: [2] |
| 145 | +normal/op_5_0: dil_conv_5x5 |
| 146 | +normal/input_5_0: [2] |
| 147 | +normal/op_5_1: sep_conv_5x5 |
| 148 | +normal/input_5_1: [4] |
| 149 | +reduce/op_2_0: dil_conv_5x5 |
| 150 | +reduce/input_2_0: [0] |
| 151 | +reduce/op_2_1: max_pool_3x3 |
| 152 | +reduce/input_2_1: [1] |
| 153 | +reduce/op_3_0: skip_connect |
| 154 | +reduce/input_3_0: [0] |
| 155 | +reduce/op_3_1: skip_connect |
| 156 | +reduce/input_3_1: [2] |
| 157 | +reduce/op_4_0: dil_conv_3x3 |
| 158 | +reduce/input_4_0: [3] |
| 159 | +reduce/op_4_1: max_pool_3x3 |
| 160 | +reduce/input_4_1: [1] |
| 161 | +reduce/op_5_0: skip_connect |
| 162 | +reduce/input_5_0: [0] |
| 163 | +reduce/op_5_1: dil_conv_5x5 |
| 164 | +reduce/input_5_1: [1] |
| 165 | + |
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