DPC++ daily 2023-05-09

sycl-nightly/20230509

[SYCL][Test E2E] Use %{build}/%{run} in Assert tests (#9366)

DPC++ daily 2023-05-08

sycl-nightly/20230508

[SYCL][Test E2E] Use %{build}/%{run} in miscellaneous tests (#9347)

DPC++ daily 2023-05-07

[SYCL] Throw for invalid reqd_work_group_size (#9237)

Also fix alignment

DPC++ daily 2023-05-06

sycl-nightly/20230506

[SYCL][Test E2E] Introduce %{build}/%{run} substitution/expansion (#9…

DPC++ daily 2023-05-05

[SYCL][NFC] Ignore GCC compatibility warning for diagnose_if (#9314)

This commit ignores the warning about GCC compatibility produced by the
use of diagnose_if in device::has and platform::has.

---------

Signed-off-by: Larsen, Steffen <steffen.larsen@intel.com>

DPC++ daily 2023-05-04

[SYCL][NFC] Update InvokeSimd E2E codeowners (#9268)

Right now it's SYCL runtime, it should be ESIMD.

Signed-off-by: Sarnie, Nick <nick.sarnie@intel.com>

DPC++ daily 2023-05-03

[SYCL] Add new FPGA loop attribute enable_loop_pipelining (#9263)

This patch adds support for new FPGA attribute called
enable_loop_pipelining, which is similar to disable_loop_pipelining.

This attribute is useful in the low-area flow, in which all loops are
unpipelined by default and the user may wish to enable loop pipelining.

The [[intel::enable_loop_pipelining]] attribute is applicable to loops
in SYCL device code. If the loop has this attribute, the LLVM IR loop
will have the llvm.loop.intel.pipelining.enable metadata, with value 1,
as shown below:

br .... !llvm.loop !0

!0 = {!1}
!1 = !{!"llvm.loop.intel.pipelining.enable", i32 1}

An error should be output if both [[intel::enable_loop_pipelining]] and
[[intel::disable_loop_pipelining]] are applied to the same loop.

---------

Signed-off-by: Soumi Manna <soumi.manna@intel.com>

DPC++ daily 2023-05-02

[Driver][SYCL] Fix crash when using libraries with -fsycl (#9276)

When performing any non-linking behaviors with -fsycl (like -c or -E)
and adding any non-compiled input value such as a library the driver
would crash due to invalid phase information.

Update the usage of the phase information to be more accurate depending
on the input (i.e. Archive)

DPC++ daily 2023-05-01

sycl-nightly/20230501

[SYCL][ESIMD] Fix failing raw_send test (#9233)

DPC++ daily 2023-04-28

sycl-nightly/20230428

[SYCL] Disable cache_config.cpp on Windows Gen9 (#9255)