From fb98894802b8f3630198586e6bc8452f90ea09f4 Mon Sep 17 00:00:00 2001 From: Wenju He Date: Mon, 7 Jul 2025 03:18:41 +0200 Subject: [PATCH 1/4] [SYCL] Change UConvert arg type to unsigned and SConvert arg type to signed To align with SPIR-V spec and SPV-IR in SPIRV-LLVM-Translator. --- clang/lib/Sema/SPIRVBuiltins.td | 4 +- libclc/test/.clang-format | 1 + libclc/test/binding/core/SConvert_Rchar.cl | 15 --- libclc/test/binding/core/SConvert_Rchar16.cl | 15 --- .../test/binding/core/SConvert_Rchar16_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rchar2.cl | 15 --- .../test/binding/core/SConvert_Rchar2_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rchar3.cl | 15 --- .../test/binding/core/SConvert_Rchar3_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rchar4.cl | 15 --- .../test/binding/core/SConvert_Rchar4_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rchar8.cl | 15 --- .../test/binding/core/SConvert_Rchar8_sat.cl | 15 --- .../test/binding/core/SConvert_Rchar_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint.cl | 15 --- libclc/test/binding/core/SConvert_Rint16.cl | 15 --- .../test/binding/core/SConvert_Rint16_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint2.cl | 15 --- .../test/binding/core/SConvert_Rint2_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint3.cl | 15 --- .../test/binding/core/SConvert_Rint3_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint4.cl | 15 --- .../test/binding/core/SConvert_Rint4_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint8.cl | 15 --- .../test/binding/core/SConvert_Rint8_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rint_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rlong.cl | 15 --- libclc/test/binding/core/SConvert_Rlong16.cl | 15 --- .../test/binding/core/SConvert_Rlong16_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rlong2.cl | 15 --- .../test/binding/core/SConvert_Rlong2_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rlong3.cl | 15 --- .../test/binding/core/SConvert_Rlong3_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rlong4.cl | 15 --- .../test/binding/core/SConvert_Rlong4_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rlong8.cl | 15 --- .../test/binding/core/SConvert_Rlong8_sat.cl | 15 --- .../test/binding/core/SConvert_Rlong_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rshort.cl | 15 --- libclc/test/binding/core/SConvert_Rshort16.cl | 15 --- .../binding/core/SConvert_Rshort16_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rshort2.cl | 15 --- .../test/binding/core/SConvert_Rshort2_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rshort3.cl | 15 --- .../test/binding/core/SConvert_Rshort3_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rshort4.cl | 15 --- .../test/binding/core/SConvert_Rshort4_sat.cl | 15 --- libclc/test/binding/core/SConvert_Rshort8.cl | 15 --- .../test/binding/core/SConvert_Rshort8_sat.cl | 15 --- .../test/binding/core/SConvert_Rshort_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar16.cl | 15 --- .../binding/core/UConvert_Ruchar16_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar2.cl | 15 --- .../test/binding/core/UConvert_Ruchar2_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar3.cl | 15 --- .../test/binding/core/UConvert_Ruchar3_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar4.cl | 15 --- .../test/binding/core/UConvert_Ruchar4_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruchar8.cl | 15 --- .../test/binding/core/UConvert_Ruchar8_sat.cl | 15 --- .../test/binding/core/UConvert_Ruchar_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruint.cl | 15 --- libclc/test/binding/core/UConvert_Ruint16.cl | 15 --- .../test/binding/core/UConvert_Ruint16_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruint2.cl | 15 --- .../test/binding/core/UConvert_Ruint2_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruint3.cl | 15 --- .../test/binding/core/UConvert_Ruint3_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruint4.cl | 15 --- .../test/binding/core/UConvert_Ruint4_sat.cl | 15 --- libclc/test/binding/core/UConvert_Ruint8.cl | 15 --- .../test/binding/core/UConvert_Ruint8_sat.cl | 15 --- .../test/binding/core/UConvert_Ruint_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rulong.cl | 15 --- libclc/test/binding/core/UConvert_Rulong16.cl | 15 --- .../binding/core/UConvert_Rulong16_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rulong2.cl | 15 --- .../test/binding/core/UConvert_Rulong2_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rulong3.cl | 15 --- .../test/binding/core/UConvert_Rulong3_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rulong4.cl | 15 --- .../test/binding/core/UConvert_Rulong4_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rulong8.cl | 15 --- .../test/binding/core/UConvert_Rulong8_sat.cl | 15 --- .../test/binding/core/UConvert_Rulong_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rushort.cl | 15 --- .../test/binding/core/UConvert_Rushort16.cl | 15 --- .../binding/core/UConvert_Rushort16_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rushort2.cl | 15 --- .../binding/core/UConvert_Rushort2_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rushort3.cl | 15 --- .../binding/core/UConvert_Rushort3_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rushort4.cl | 15 --- .../binding/core/UConvert_Rushort4_sat.cl | 15 --- libclc/test/binding/core/UConvert_Rushort8.cl | 15 --- .../binding/core/UConvert_Rushort8_sat.cl | 15 --- .../test/binding/core/UConvert_Rushort_sat.cl | 15 --- libclc/test/binding/ocl/ldexp.cl | 113 ------------------ libclc/test/binding/ocl/vload_half.cl | 6 + .../test/binding/ocl/vload_halfn_Rfloat16.cl | 6 + .../test/binding/ocl/vload_halfn_Rfloat2.cl | 6 + .../test/binding/ocl/vload_halfn_Rfloat3.cl | 6 + .../test/binding/ocl/vload_halfn_Rfloat4.cl | 6 + .../test/binding/ocl/vload_halfn_Rfloat8.cl | 6 + .../test/binding/ocl/vloada_halfn_Rfloat16.cl | 6 + .../test/binding/ocl/vloada_halfn_Rfloat2.cl | 6 + .../test/binding/ocl/vloada_halfn_Rfloat3.cl | 6 + .../test/binding/ocl/vloada_halfn_Rfloat4.cl | 6 + .../test/binding/ocl/vloada_halfn_Rfloat8.cl | 6 + libclc/test/binding/ocl/vloadn_Rchar16.cl | 6 + libclc/test/binding/ocl/vloadn_Rchar2.cl | 6 + libclc/test/binding/ocl/vloadn_Rchar3.cl | 6 + libclc/test/binding/ocl/vloadn_Rchar4.cl | 6 + libclc/test/binding/ocl/vloadn_Rchar8.cl | 6 + libclc/test/binding/ocl/vloadn_Rdouble16.cl | 6 + libclc/test/binding/ocl/vloadn_Rdouble2.cl | 6 + libclc/test/binding/ocl/vloadn_Rdouble3.cl | 6 + libclc/test/binding/ocl/vloadn_Rdouble4.cl | 6 + libclc/test/binding/ocl/vloadn_Rdouble8.cl | 6 + libclc/test/binding/ocl/vloadn_Rfloat16.cl | 6 + libclc/test/binding/ocl/vloadn_Rfloat2.cl | 6 + libclc/test/binding/ocl/vloadn_Rfloat3.cl | 6 + libclc/test/binding/ocl/vloadn_Rfloat4.cl | 6 + libclc/test/binding/ocl/vloadn_Rfloat8.cl | 6 + libclc/test/binding/ocl/vloadn_Rhalf16.cl | 6 + libclc/test/binding/ocl/vloadn_Rhalf2.cl | 6 + libclc/test/binding/ocl/vloadn_Rhalf3.cl | 6 + libclc/test/binding/ocl/vloadn_Rhalf4.cl | 6 + libclc/test/binding/ocl/vloadn_Rhalf8.cl | 6 + libclc/test/binding/ocl/vloadn_Rint16.cl | 6 + libclc/test/binding/ocl/vloadn_Rint2.cl | 6 + libclc/test/binding/ocl/vloadn_Rint3.cl | 6 + libclc/test/binding/ocl/vloadn_Rint4.cl | 6 + libclc/test/binding/ocl/vloadn_Rint8.cl | 6 + libclc/test/binding/ocl/vloadn_Rlong16.cl | 6 + libclc/test/binding/ocl/vloadn_Rlong2.cl | 6 + libclc/test/binding/ocl/vloadn_Rlong3.cl | 6 + libclc/test/binding/ocl/vloadn_Rlong4.cl | 6 + libclc/test/binding/ocl/vloadn_Rlong8.cl | 6 + libclc/test/binding/ocl/vloadn_Rshort16.cl | 6 + libclc/test/binding/ocl/vloadn_Rshort2.cl | 6 + libclc/test/binding/ocl/vloadn_Rshort3.cl | 6 + libclc/test/binding/ocl/vloadn_Rshort4.cl | 6 + libclc/test/binding/ocl/vloadn_Rshort8.cl | 6 + libclc/test/binding/ocl/vloadn_Ruchar16.cl | 6 + libclc/test/binding/ocl/vloadn_Ruchar2.cl | 6 + libclc/test/binding/ocl/vloadn_Ruchar3.cl | 6 + libclc/test/binding/ocl/vloadn_Ruchar4.cl | 6 + libclc/test/binding/ocl/vloadn_Ruchar8.cl | 6 + libclc/test/binding/ocl/vloadn_Ruint16.cl | 6 + libclc/test/binding/ocl/vloadn_Ruint2.cl | 6 + libclc/test/binding/ocl/vloadn_Ruint3.cl | 6 + libclc/test/binding/ocl/vloadn_Ruint4.cl | 6 + libclc/test/binding/ocl/vloadn_Ruint8.cl | 6 + libclc/test/binding/ocl/vloadn_Rulong16.cl | 6 + libclc/test/binding/ocl/vloadn_Rulong2.cl | 6 + libclc/test/binding/ocl/vloadn_Rulong3.cl | 6 + libclc/test/binding/ocl/vloadn_Rulong4.cl | 6 + libclc/test/binding/ocl/vloadn_Rulong8.cl | 6 + libclc/test/binding/ocl/vloadn_Rushort16.cl | 6 + libclc/test/binding/ocl/vloadn_Rushort2.cl | 6 + libclc/test/binding/ocl/vloadn_Rushort3.cl | 6 + libclc/test/binding/ocl/vloadn_Rushort4.cl | 6 + libclc/test/binding/ocl/vloadn_Rushort8.cl | 6 + libclc/test/binding/ocl/vstore_half.cl | 6 + libclc/test/binding/ocl/vstore_half_r.cl | 6 + libclc/test/binding/ocl/vstore_halfn.cl | 6 + libclc/test/binding/ocl/vstore_halfn_r.cl | 6 + libclc/test/binding/ocl/vstorea_halfn.cl | 6 + libclc/test/binding/ocl/vstorea_halfn_r.cl | 6 + libclc/test/binding/ocl/vstoren.cl | 6 + 172 files changed, 442 insertions(+), 1554 deletions(-) create mode 100644 libclc/test/.clang-format diff --git a/clang/lib/Sema/SPIRVBuiltins.td b/clang/lib/Sema/SPIRVBuiltins.td index e226e3b223e17..e5019b5202a43 100644 --- a/clang/lib/Sema/SPIRVBuiltins.td +++ b/clang/lib/Sema/SPIRVBuiltins.td @@ -803,7 +803,7 @@ foreach rnd = ["", "_rte", "_rtn", "_rtp", "_rtz"] in { } foreach sat = ["", "_sat"] in { - foreach InType = TLAllInts.List in { + foreach InType = TLUnsignedInts.List in { foreach OutType = TLUnsignedInts.List in { if !ne(OutType.ElementSize, InType.ElementSize) then { def : SPVBuiltin<"UConvert_R" # OutType.Name # sat, [OutType, InType], Attr.Const>; @@ -814,6 +814,8 @@ foreach sat = ["", "_sat"] in { } } } + } + foreach InType = TLSignedInts.List in { foreach OutType = TLSignedInts.List in { if !ne(OutType.ElementSize, InType.ElementSize) then { def : SPVBuiltin<"SConvert_R" # OutType.Name # sat, [OutType, InType], Attr.Const>; diff --git a/libclc/test/.clang-format b/libclc/test/.clang-format new file mode 100644 index 0000000000000..e3845288a2aec --- /dev/null +++ b/libclc/test/.clang-format @@ -0,0 +1 @@ +DisableFormat: true diff --git a/libclc/test/binding/core/SConvert_Rchar.cl b/libclc/test/binding/core/SConvert_Rchar.cl index 1d0335f3c8770..f543785653b90 100644 --- a/libclc/test/binding/core/SConvert_Rchar.cl +++ b/libclc/test/binding/core/SConvert_Rchar.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar(__clc_int16_t args_0) { return __spirv_SConvert_Rchar(args_0); } -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar(__clc_uint16_t args_0) { - return __spirv_SConvert_Rchar(args_0); -} - __attribute__((overloadable)) __clc_int8_t test___spirv_SConvert_Rchar(__clc_int32_t args_0) { return __spirv_SConvert_Rchar(args_0); } -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar(__clc_uint32_t args_0) { - return __spirv_SConvert_Rchar(args_0); -} - __attribute__((overloadable)) __clc_int8_t test___spirv_SConvert_Rchar(__clc_int64_t args_0) { return __spirv_SConvert_Rchar(args_0); } - -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar(__clc_uint64_t args_0) { - return __spirv_SConvert_Rchar(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar16.cl b/libclc/test/binding/core/SConvert_Rchar16.cl index f555bce4634f2..e386c2ce2acef 100644 --- a/libclc/test/binding/core/SConvert_Rchar16.cl +++ b/libclc/test/binding/core/SConvert_Rchar16.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar16(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rchar16(args_0); } -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rchar16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int8_t test___spirv_SConvert_Rchar16(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rchar16(args_0); } -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rchar16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int8_t test___spirv_SConvert_Rchar16(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rchar16(args_0); } - -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rchar16(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar16_sat.cl b/libclc/test/binding/core/SConvert_Rchar16_sat.cl index 10aa6353b6b0c..1b4c7862a5670 100644 --- a/libclc/test/binding/core/SConvert_Rchar16_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar16_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar16_sat(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rchar16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rchar16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int8_t test___spirv_SConvert_Rchar16_sat(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rchar16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rchar16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int8_t test___spirv_SConvert_Rchar16_sat(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rchar16_sat(args_0); } - -__attribute__((overloadable)) __clc_vec16_int8_t -test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rchar16_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar2.cl b/libclc/test/binding/core/SConvert_Rchar2.cl index de89f03f9f9b4..a131483b00e51 100644 --- a/libclc/test/binding/core/SConvert_Rchar2.cl +++ b/libclc/test/binding/core/SConvert_Rchar2.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar2(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rchar2(args_0); } -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rchar2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int8_t test___spirv_SConvert_Rchar2(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rchar2(args_0); } -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rchar2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int8_t test___spirv_SConvert_Rchar2(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rchar2(args_0); } - -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rchar2(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar2_sat.cl b/libclc/test/binding/core/SConvert_Rchar2_sat.cl index 6434dc7f9f393..ac80b8e579bc9 100644 --- a/libclc/test/binding/core/SConvert_Rchar2_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar2_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar2_sat(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rchar2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rchar2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int8_t test___spirv_SConvert_Rchar2_sat(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rchar2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rchar2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int8_t test___spirv_SConvert_Rchar2_sat(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rchar2_sat(args_0); } - -__attribute__((overloadable)) __clc_vec2_int8_t -test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rchar2_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar3.cl b/libclc/test/binding/core/SConvert_Rchar3.cl index 4750ce91ecbac..2e9074722d145 100644 --- a/libclc/test/binding/core/SConvert_Rchar3.cl +++ b/libclc/test/binding/core/SConvert_Rchar3.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar3(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rchar3(args_0); } -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rchar3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int8_t test___spirv_SConvert_Rchar3(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rchar3(args_0); } -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rchar3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int8_t test___spirv_SConvert_Rchar3(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rchar3(args_0); } - -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rchar3(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar3_sat.cl b/libclc/test/binding/core/SConvert_Rchar3_sat.cl index 53924549a36b0..1fae9aa669687 100644 --- a/libclc/test/binding/core/SConvert_Rchar3_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar3_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar3_sat(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rchar3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rchar3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int8_t test___spirv_SConvert_Rchar3_sat(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rchar3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rchar3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int8_t test___spirv_SConvert_Rchar3_sat(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rchar3_sat(args_0); } - -__attribute__((overloadable)) __clc_vec3_int8_t -test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rchar3_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar4.cl b/libclc/test/binding/core/SConvert_Rchar4.cl index b0b9a116a1b30..d611bf0f94993 100644 --- a/libclc/test/binding/core/SConvert_Rchar4.cl +++ b/libclc/test/binding/core/SConvert_Rchar4.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar4(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rchar4(args_0); } -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rchar4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int8_t test___spirv_SConvert_Rchar4(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rchar4(args_0); } -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rchar4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int8_t test___spirv_SConvert_Rchar4(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rchar4(args_0); } - -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rchar4(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar4_sat.cl b/libclc/test/binding/core/SConvert_Rchar4_sat.cl index 3543744078086..4e4e6ca0cd2d8 100644 --- a/libclc/test/binding/core/SConvert_Rchar4_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar4_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar4_sat(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rchar4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rchar4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int8_t test___spirv_SConvert_Rchar4_sat(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rchar4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rchar4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int8_t test___spirv_SConvert_Rchar4_sat(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rchar4_sat(args_0); } - -__attribute__((overloadable)) __clc_vec4_int8_t -test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rchar4_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar8.cl b/libclc/test/binding/core/SConvert_Rchar8.cl index 726f78ab63428..0fd794ba26871 100644 --- a/libclc/test/binding/core/SConvert_Rchar8.cl +++ b/libclc/test/binding/core/SConvert_Rchar8.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar8(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rchar8(args_0); } -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rchar8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int8_t test___spirv_SConvert_Rchar8(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rchar8(args_0); } -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rchar8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int8_t test___spirv_SConvert_Rchar8(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rchar8(args_0); } - -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rchar8(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar8_sat.cl b/libclc/test/binding/core/SConvert_Rchar8_sat.cl index 25c080d5ebdbd..40a888e084a34 100644 --- a/libclc/test/binding/core/SConvert_Rchar8_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar8_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar8_sat(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rchar8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rchar8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int8_t test___spirv_SConvert_Rchar8_sat(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rchar8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rchar8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int8_t test___spirv_SConvert_Rchar8_sat(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rchar8_sat(args_0); } - -__attribute__((overloadable)) __clc_vec8_int8_t -test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rchar8_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rchar_sat.cl b/libclc/test/binding/core/SConvert_Rchar_sat.cl index df7a87eb5379b..d8001fc42b817 100644 --- a/libclc/test/binding/core/SConvert_Rchar_sat.cl +++ b/libclc/test/binding/core/SConvert_Rchar_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rchar_sat(__clc_int16_t args_0) { return __spirv_SConvert_Rchar_sat(args_0); } -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar_sat(__clc_uint16_t args_0) { - return __spirv_SConvert_Rchar_sat(args_0); -} - __attribute__((overloadable)) __clc_int8_t test___spirv_SConvert_Rchar_sat(__clc_int32_t args_0) { return __spirv_SConvert_Rchar_sat(args_0); } -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar_sat(__clc_uint32_t args_0) { - return __spirv_SConvert_Rchar_sat(args_0); -} - __attribute__((overloadable)) __clc_int8_t test___spirv_SConvert_Rchar_sat(__clc_int64_t args_0) { return __spirv_SConvert_Rchar_sat(args_0); } - -__attribute__((overloadable)) __clc_int8_t -test___spirv_SConvert_Rchar_sat(__clc_uint64_t args_0) { - return __spirv_SConvert_Rchar_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint.cl b/libclc/test/binding/core/SConvert_Rint.cl index 513a2be992ac8..e05de9622c544 100644 --- a/libclc/test/binding/core/SConvert_Rint.cl +++ b/libclc/test/binding/core/SConvert_Rint.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint(__clc_int8_t args_0) { return __spirv_SConvert_Rint(args_0); } -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint(__clc_uint8_t args_0) { - return __spirv_SConvert_Rint(args_0); -} - __attribute__((overloadable)) __clc_int32_t test___spirv_SConvert_Rint(__clc_int16_t args_0) { return __spirv_SConvert_Rint(args_0); } -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint(__clc_uint16_t args_0) { - return __spirv_SConvert_Rint(args_0); -} - __attribute__((overloadable)) __clc_int32_t test___spirv_SConvert_Rint(__clc_int64_t args_0) { return __spirv_SConvert_Rint(args_0); } - -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint(__clc_uint64_t args_0) { - return __spirv_SConvert_Rint(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint16.cl b/libclc/test/binding/core/SConvert_Rint16.cl index 51c1b653aa0e4..1850596258482 100644 --- a/libclc/test/binding/core/SConvert_Rint16.cl +++ b/libclc/test/binding/core/SConvert_Rint16.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint16(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rint16(args_0); } -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rint16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int32_t test___spirv_SConvert_Rint16(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rint16(args_0); } -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rint16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int32_t test___spirv_SConvert_Rint16(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rint16(args_0); } - -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rint16(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint16_sat.cl b/libclc/test/binding/core/SConvert_Rint16_sat.cl index 5b8a60945c901..63f160275b28a 100644 --- a/libclc/test/binding/core/SConvert_Rint16_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint16_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint16_sat(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rint16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16_sat(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rint16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int32_t test___spirv_SConvert_Rint16_sat(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rint16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16_sat(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rint16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int32_t test___spirv_SConvert_Rint16_sat(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rint16_sat(args_0); } - -__attribute__((overloadable)) __clc_vec16_int32_t -test___spirv_SConvert_Rint16_sat(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rint16_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint2.cl b/libclc/test/binding/core/SConvert_Rint2.cl index 0ad887ba0f7a5..27b5eda64f64b 100644 --- a/libclc/test/binding/core/SConvert_Rint2.cl +++ b/libclc/test/binding/core/SConvert_Rint2.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint2(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rint2(args_0); } -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rint2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int32_t test___spirv_SConvert_Rint2(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rint2(args_0); } -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rint2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int32_t test___spirv_SConvert_Rint2(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rint2(args_0); } - -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rint2(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint2_sat.cl b/libclc/test/binding/core/SConvert_Rint2_sat.cl index 954a2e069a0b4..afdb051bd9368 100644 --- a/libclc/test/binding/core/SConvert_Rint2_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint2_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint2_sat(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rint2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2_sat(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rint2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int32_t test___spirv_SConvert_Rint2_sat(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rint2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2_sat(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rint2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int32_t test___spirv_SConvert_Rint2_sat(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rint2_sat(args_0); } - -__attribute__((overloadable)) __clc_vec2_int32_t -test___spirv_SConvert_Rint2_sat(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rint2_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint3.cl b/libclc/test/binding/core/SConvert_Rint3.cl index d397afbb9c08b..a4fc6a73d6deb 100644 --- a/libclc/test/binding/core/SConvert_Rint3.cl +++ b/libclc/test/binding/core/SConvert_Rint3.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint3(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rint3(args_0); } -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rint3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int32_t test___spirv_SConvert_Rint3(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rint3(args_0); } -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rint3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int32_t test___spirv_SConvert_Rint3(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rint3(args_0); } - -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rint3(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint3_sat.cl b/libclc/test/binding/core/SConvert_Rint3_sat.cl index 890b49b722f82..72189ea1ee55c 100644 --- a/libclc/test/binding/core/SConvert_Rint3_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint3_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint3_sat(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rint3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3_sat(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rint3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int32_t test___spirv_SConvert_Rint3_sat(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rint3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3_sat(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rint3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int32_t test___spirv_SConvert_Rint3_sat(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rint3_sat(args_0); } - -__attribute__((overloadable)) __clc_vec3_int32_t -test___spirv_SConvert_Rint3_sat(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rint3_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint4.cl b/libclc/test/binding/core/SConvert_Rint4.cl index 39364261baefb..a88749c820af9 100644 --- a/libclc/test/binding/core/SConvert_Rint4.cl +++ b/libclc/test/binding/core/SConvert_Rint4.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint4(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rint4(args_0); } -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rint4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int32_t test___spirv_SConvert_Rint4(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rint4(args_0); } -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rint4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int32_t test___spirv_SConvert_Rint4(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rint4(args_0); } - -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rint4(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint4_sat.cl b/libclc/test/binding/core/SConvert_Rint4_sat.cl index a8f2403af3830..b27abb51a0885 100644 --- a/libclc/test/binding/core/SConvert_Rint4_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint4_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint4_sat(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rint4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4_sat(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rint4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int32_t test___spirv_SConvert_Rint4_sat(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rint4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4_sat(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rint4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int32_t test___spirv_SConvert_Rint4_sat(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rint4_sat(args_0); } - -__attribute__((overloadable)) __clc_vec4_int32_t -test___spirv_SConvert_Rint4_sat(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rint4_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint8.cl b/libclc/test/binding/core/SConvert_Rint8.cl index d1fa1faa1887e..88f28e656c511 100644 --- a/libclc/test/binding/core/SConvert_Rint8.cl +++ b/libclc/test/binding/core/SConvert_Rint8.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint8(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rint8(args_0); } -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rint8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int32_t test___spirv_SConvert_Rint8(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rint8(args_0); } -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rint8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int32_t test___spirv_SConvert_Rint8(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rint8(args_0); } - -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rint8(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint8_sat.cl b/libclc/test/binding/core/SConvert_Rint8_sat.cl index afce11024d42f..b481e1f220d9b 100644 --- a/libclc/test/binding/core/SConvert_Rint8_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint8_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint8_sat(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rint8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8_sat(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rint8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int32_t test___spirv_SConvert_Rint8_sat(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rint8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8_sat(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rint8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int32_t test___spirv_SConvert_Rint8_sat(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rint8_sat(args_0); } - -__attribute__((overloadable)) __clc_vec8_int32_t -test___spirv_SConvert_Rint8_sat(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rint8_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rint_sat.cl b/libclc/test/binding/core/SConvert_Rint_sat.cl index c49d6b9636ac4..7e27164c89054 100644 --- a/libclc/test/binding/core/SConvert_Rint_sat.cl +++ b/libclc/test/binding/core/SConvert_Rint_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rint_sat(__clc_int8_t args_0) { return __spirv_SConvert_Rint_sat(args_0); } -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint_sat(__clc_uint8_t args_0) { - return __spirv_SConvert_Rint_sat(args_0); -} - __attribute__((overloadable)) __clc_int32_t test___spirv_SConvert_Rint_sat(__clc_int16_t args_0) { return __spirv_SConvert_Rint_sat(args_0); } -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint_sat(__clc_uint16_t args_0) { - return __spirv_SConvert_Rint_sat(args_0); -} - __attribute__((overloadable)) __clc_int32_t test___spirv_SConvert_Rint_sat(__clc_int64_t args_0) { return __spirv_SConvert_Rint_sat(args_0); } - -__attribute__((overloadable)) __clc_int32_t -test___spirv_SConvert_Rint_sat(__clc_uint64_t args_0) { - return __spirv_SConvert_Rint_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong.cl b/libclc/test/binding/core/SConvert_Rlong.cl index d408bed90a40c..65dd7277965a9 100644 --- a/libclc/test/binding/core/SConvert_Rlong.cl +++ b/libclc/test/binding/core/SConvert_Rlong.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong(__clc_int8_t args_0) { return __spirv_SConvert_Rlong(args_0); } -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong(__clc_uint8_t args_0) { - return __spirv_SConvert_Rlong(args_0); -} - __attribute__((overloadable)) __clc_int64_t test___spirv_SConvert_Rlong(__clc_int16_t args_0) { return __spirv_SConvert_Rlong(args_0); } -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong(__clc_uint16_t args_0) { - return __spirv_SConvert_Rlong(args_0); -} - __attribute__((overloadable)) __clc_int64_t test___spirv_SConvert_Rlong(__clc_int32_t args_0) { return __spirv_SConvert_Rlong(args_0); } - -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong(__clc_uint32_t args_0) { - return __spirv_SConvert_Rlong(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong16.cl b/libclc/test/binding/core/SConvert_Rlong16.cl index aa824aeb508a7..4658795322859 100644 --- a/libclc/test/binding/core/SConvert_Rlong16.cl +++ b/libclc/test/binding/core/SConvert_Rlong16.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong16(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rlong16(args_0); } -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rlong16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int64_t test___spirv_SConvert_Rlong16(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rlong16(args_0); } -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rlong16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int64_t test___spirv_SConvert_Rlong16(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rlong16(args_0); } - -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rlong16(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong16_sat.cl b/libclc/test/binding/core/SConvert_Rlong16_sat.cl index 61ba7123ac189..a77d106c63648 100644 --- a/libclc/test/binding/core/SConvert_Rlong16_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong16_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong16_sat(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rlong16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rlong16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int64_t test___spirv_SConvert_Rlong16_sat(__clc_vec16_int16_t args_0) { return __spirv_SConvert_Rlong16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint16_t args_0) { - return __spirv_SConvert_Rlong16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int64_t test___spirv_SConvert_Rlong16_sat(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rlong16_sat(args_0); } - -__attribute__((overloadable)) __clc_vec16_int64_t -test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rlong16_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong2.cl b/libclc/test/binding/core/SConvert_Rlong2.cl index 6a88381d9b732..362765b9ae21d 100644 --- a/libclc/test/binding/core/SConvert_Rlong2.cl +++ b/libclc/test/binding/core/SConvert_Rlong2.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong2(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rlong2(args_0); } -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rlong2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int64_t test___spirv_SConvert_Rlong2(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rlong2(args_0); } -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rlong2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int64_t test___spirv_SConvert_Rlong2(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rlong2(args_0); } - -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rlong2(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong2_sat.cl b/libclc/test/binding/core/SConvert_Rlong2_sat.cl index 66dfa5004b021..0873a00471cc8 100644 --- a/libclc/test/binding/core/SConvert_Rlong2_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong2_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong2_sat(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rlong2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rlong2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int64_t test___spirv_SConvert_Rlong2_sat(__clc_vec2_int16_t args_0) { return __spirv_SConvert_Rlong2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint16_t args_0) { - return __spirv_SConvert_Rlong2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int64_t test___spirv_SConvert_Rlong2_sat(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rlong2_sat(args_0); } - -__attribute__((overloadable)) __clc_vec2_int64_t -test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rlong2_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong3.cl b/libclc/test/binding/core/SConvert_Rlong3.cl index 245be22561990..85a98b955759b 100644 --- a/libclc/test/binding/core/SConvert_Rlong3.cl +++ b/libclc/test/binding/core/SConvert_Rlong3.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong3(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rlong3(args_0); } -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rlong3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int64_t test___spirv_SConvert_Rlong3(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rlong3(args_0); } -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rlong3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int64_t test___spirv_SConvert_Rlong3(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rlong3(args_0); } - -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rlong3(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong3_sat.cl b/libclc/test/binding/core/SConvert_Rlong3_sat.cl index cf150aef8a2aa..2d85b02436942 100644 --- a/libclc/test/binding/core/SConvert_Rlong3_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong3_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong3_sat(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rlong3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rlong3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int64_t test___spirv_SConvert_Rlong3_sat(__clc_vec3_int16_t args_0) { return __spirv_SConvert_Rlong3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint16_t args_0) { - return __spirv_SConvert_Rlong3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int64_t test___spirv_SConvert_Rlong3_sat(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rlong3_sat(args_0); } - -__attribute__((overloadable)) __clc_vec3_int64_t -test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rlong3_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong4.cl b/libclc/test/binding/core/SConvert_Rlong4.cl index ace6e0e4e5b35..2fde9723f311d 100644 --- a/libclc/test/binding/core/SConvert_Rlong4.cl +++ b/libclc/test/binding/core/SConvert_Rlong4.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong4(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rlong4(args_0); } -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rlong4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int64_t test___spirv_SConvert_Rlong4(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rlong4(args_0); } -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rlong4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int64_t test___spirv_SConvert_Rlong4(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rlong4(args_0); } - -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rlong4(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong4_sat.cl b/libclc/test/binding/core/SConvert_Rlong4_sat.cl index 83262c2ecf2fa..9df2c3963d76c 100644 --- a/libclc/test/binding/core/SConvert_Rlong4_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong4_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong4_sat(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rlong4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rlong4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int64_t test___spirv_SConvert_Rlong4_sat(__clc_vec4_int16_t args_0) { return __spirv_SConvert_Rlong4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint16_t args_0) { - return __spirv_SConvert_Rlong4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int64_t test___spirv_SConvert_Rlong4_sat(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rlong4_sat(args_0); } - -__attribute__((overloadable)) __clc_vec4_int64_t -test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rlong4_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong8.cl b/libclc/test/binding/core/SConvert_Rlong8.cl index 59b55924a2a32..b76137bd4e14c 100644 --- a/libclc/test/binding/core/SConvert_Rlong8.cl +++ b/libclc/test/binding/core/SConvert_Rlong8.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong8(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rlong8(args_0); } -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rlong8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int64_t test___spirv_SConvert_Rlong8(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rlong8(args_0); } -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rlong8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int64_t test___spirv_SConvert_Rlong8(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rlong8(args_0); } - -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rlong8(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong8_sat.cl b/libclc/test/binding/core/SConvert_Rlong8_sat.cl index d1d35ee1fc89f..86f6326bdfd67 100644 --- a/libclc/test/binding/core/SConvert_Rlong8_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong8_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong8_sat(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rlong8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rlong8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int64_t test___spirv_SConvert_Rlong8_sat(__clc_vec8_int16_t args_0) { return __spirv_SConvert_Rlong8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint16_t args_0) { - return __spirv_SConvert_Rlong8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int64_t test___spirv_SConvert_Rlong8_sat(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rlong8_sat(args_0); } - -__attribute__((overloadable)) __clc_vec8_int64_t -test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rlong8_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rlong_sat.cl b/libclc/test/binding/core/SConvert_Rlong_sat.cl index 25cea660fa426..125859c25122e 100644 --- a/libclc/test/binding/core/SConvert_Rlong_sat.cl +++ b/libclc/test/binding/core/SConvert_Rlong_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rlong_sat(__clc_int8_t args_0) { return __spirv_SConvert_Rlong_sat(args_0); } -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong_sat(__clc_uint8_t args_0) { - return __spirv_SConvert_Rlong_sat(args_0); -} - __attribute__((overloadable)) __clc_int64_t test___spirv_SConvert_Rlong_sat(__clc_int16_t args_0) { return __spirv_SConvert_Rlong_sat(args_0); } -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong_sat(__clc_uint16_t args_0) { - return __spirv_SConvert_Rlong_sat(args_0); -} - __attribute__((overloadable)) __clc_int64_t test___spirv_SConvert_Rlong_sat(__clc_int32_t args_0) { return __spirv_SConvert_Rlong_sat(args_0); } - -__attribute__((overloadable)) __clc_int64_t -test___spirv_SConvert_Rlong_sat(__clc_uint32_t args_0) { - return __spirv_SConvert_Rlong_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort.cl b/libclc/test/binding/core/SConvert_Rshort.cl index f2d1db1bffca2..1baaf2e9e9ef1 100644 --- a/libclc/test/binding/core/SConvert_Rshort.cl +++ b/libclc/test/binding/core/SConvert_Rshort.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort(__clc_int8_t args_0) { return __spirv_SConvert_Rshort(args_0); } -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort(__clc_uint8_t args_0) { - return __spirv_SConvert_Rshort(args_0); -} - __attribute__((overloadable)) __clc_int16_t test___spirv_SConvert_Rshort(__clc_int32_t args_0) { return __spirv_SConvert_Rshort(args_0); } -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort(__clc_uint32_t args_0) { - return __spirv_SConvert_Rshort(args_0); -} - __attribute__((overloadable)) __clc_int16_t test___spirv_SConvert_Rshort(__clc_int64_t args_0) { return __spirv_SConvert_Rshort(args_0); } - -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort(__clc_uint64_t args_0) { - return __spirv_SConvert_Rshort(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort16.cl b/libclc/test/binding/core/SConvert_Rshort16.cl index 7430a99185746..e79d8357efbf8 100644 --- a/libclc/test/binding/core/SConvert_Rshort16.cl +++ b/libclc/test/binding/core/SConvert_Rshort16.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort16(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rshort16(args_0); } -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rshort16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int16_t test___spirv_SConvert_Rshort16(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rshort16(args_0); } -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rshort16(args_0); -} - __attribute__((overloadable)) __clc_vec16_int16_t test___spirv_SConvert_Rshort16(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rshort16(args_0); } - -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rshort16(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort16_sat.cl b/libclc/test/binding/core/SConvert_Rshort16_sat.cl index 10e351d6878b5..e856cc7177a11 100644 --- a/libclc/test/binding/core/SConvert_Rshort16_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort16_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort16_sat(__clc_vec16_int8_t args_0) { return __spirv_SConvert_Rshort16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint8_t args_0) { - return __spirv_SConvert_Rshort16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int16_t test___spirv_SConvert_Rshort16_sat(__clc_vec16_int32_t args_0) { return __spirv_SConvert_Rshort16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint32_t args_0) { - return __spirv_SConvert_Rshort16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_int16_t test___spirv_SConvert_Rshort16_sat(__clc_vec16_int64_t args_0) { return __spirv_SConvert_Rshort16_sat(args_0); } - -__attribute__((overloadable)) __clc_vec16_int16_t -test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint64_t args_0) { - return __spirv_SConvert_Rshort16_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort2.cl b/libclc/test/binding/core/SConvert_Rshort2.cl index 3953754fbe237..8376255609bba 100644 --- a/libclc/test/binding/core/SConvert_Rshort2.cl +++ b/libclc/test/binding/core/SConvert_Rshort2.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort2(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rshort2(args_0); } -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rshort2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int16_t test___spirv_SConvert_Rshort2(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rshort2(args_0); } -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rshort2(args_0); -} - __attribute__((overloadable)) __clc_vec2_int16_t test___spirv_SConvert_Rshort2(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rshort2(args_0); } - -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rshort2(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort2_sat.cl b/libclc/test/binding/core/SConvert_Rshort2_sat.cl index c78eb950396f2..374a369dec5fe 100644 --- a/libclc/test/binding/core/SConvert_Rshort2_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort2_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort2_sat(__clc_vec2_int8_t args_0) { return __spirv_SConvert_Rshort2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint8_t args_0) { - return __spirv_SConvert_Rshort2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int16_t test___spirv_SConvert_Rshort2_sat(__clc_vec2_int32_t args_0) { return __spirv_SConvert_Rshort2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint32_t args_0) { - return __spirv_SConvert_Rshort2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_int16_t test___spirv_SConvert_Rshort2_sat(__clc_vec2_int64_t args_0) { return __spirv_SConvert_Rshort2_sat(args_0); } - -__attribute__((overloadable)) __clc_vec2_int16_t -test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint64_t args_0) { - return __spirv_SConvert_Rshort2_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort3.cl b/libclc/test/binding/core/SConvert_Rshort3.cl index 74434a0646bbf..d1149445908d7 100644 --- a/libclc/test/binding/core/SConvert_Rshort3.cl +++ b/libclc/test/binding/core/SConvert_Rshort3.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort3(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rshort3(args_0); } -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rshort3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int16_t test___spirv_SConvert_Rshort3(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rshort3(args_0); } -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rshort3(args_0); -} - __attribute__((overloadable)) __clc_vec3_int16_t test___spirv_SConvert_Rshort3(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rshort3(args_0); } - -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rshort3(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort3_sat.cl b/libclc/test/binding/core/SConvert_Rshort3_sat.cl index 777f829cdde25..8e578be2575cb 100644 --- a/libclc/test/binding/core/SConvert_Rshort3_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort3_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort3_sat(__clc_vec3_int8_t args_0) { return __spirv_SConvert_Rshort3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint8_t args_0) { - return __spirv_SConvert_Rshort3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int16_t test___spirv_SConvert_Rshort3_sat(__clc_vec3_int32_t args_0) { return __spirv_SConvert_Rshort3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint32_t args_0) { - return __spirv_SConvert_Rshort3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_int16_t test___spirv_SConvert_Rshort3_sat(__clc_vec3_int64_t args_0) { return __spirv_SConvert_Rshort3_sat(args_0); } - -__attribute__((overloadable)) __clc_vec3_int16_t -test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint64_t args_0) { - return __spirv_SConvert_Rshort3_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort4.cl b/libclc/test/binding/core/SConvert_Rshort4.cl index a25edf38d15f9..21ed598dc7868 100644 --- a/libclc/test/binding/core/SConvert_Rshort4.cl +++ b/libclc/test/binding/core/SConvert_Rshort4.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort4(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rshort4(args_0); } -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rshort4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int16_t test___spirv_SConvert_Rshort4(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rshort4(args_0); } -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rshort4(args_0); -} - __attribute__((overloadable)) __clc_vec4_int16_t test___spirv_SConvert_Rshort4(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rshort4(args_0); } - -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rshort4(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort4_sat.cl b/libclc/test/binding/core/SConvert_Rshort4_sat.cl index 2f3d90b908a25..49b21eff09cc5 100644 --- a/libclc/test/binding/core/SConvert_Rshort4_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort4_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort4_sat(__clc_vec4_int8_t args_0) { return __spirv_SConvert_Rshort4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint8_t args_0) { - return __spirv_SConvert_Rshort4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int16_t test___spirv_SConvert_Rshort4_sat(__clc_vec4_int32_t args_0) { return __spirv_SConvert_Rshort4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint32_t args_0) { - return __spirv_SConvert_Rshort4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_int16_t test___spirv_SConvert_Rshort4_sat(__clc_vec4_int64_t args_0) { return __spirv_SConvert_Rshort4_sat(args_0); } - -__attribute__((overloadable)) __clc_vec4_int16_t -test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint64_t args_0) { - return __spirv_SConvert_Rshort4_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort8.cl b/libclc/test/binding/core/SConvert_Rshort8.cl index 9ff8e41a7e7c3..c592d8a9979e9 100644 --- a/libclc/test/binding/core/SConvert_Rshort8.cl +++ b/libclc/test/binding/core/SConvert_Rshort8.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort8(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rshort8(args_0); } -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rshort8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int16_t test___spirv_SConvert_Rshort8(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rshort8(args_0); } -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rshort8(args_0); -} - __attribute__((overloadable)) __clc_vec8_int16_t test___spirv_SConvert_Rshort8(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rshort8(args_0); } - -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rshort8(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort8_sat.cl b/libclc/test/binding/core/SConvert_Rshort8_sat.cl index eeedbbcf341ae..7eced4114bc57 100644 --- a/libclc/test/binding/core/SConvert_Rshort8_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort8_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort8_sat(__clc_vec8_int8_t args_0) { return __spirv_SConvert_Rshort8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint8_t args_0) { - return __spirv_SConvert_Rshort8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int16_t test___spirv_SConvert_Rshort8_sat(__clc_vec8_int32_t args_0) { return __spirv_SConvert_Rshort8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint32_t args_0) { - return __spirv_SConvert_Rshort8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_int16_t test___spirv_SConvert_Rshort8_sat(__clc_vec8_int64_t args_0) { return __spirv_SConvert_Rshort8_sat(args_0); } - -__attribute__((overloadable)) __clc_vec8_int16_t -test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint64_t args_0) { - return __spirv_SConvert_Rshort8_sat(args_0); -} diff --git a/libclc/test/binding/core/SConvert_Rshort_sat.cl b/libclc/test/binding/core/SConvert_Rshort_sat.cl index 15d34b3aec218..48d83cf5049c9 100644 --- a/libclc/test/binding/core/SConvert_Rshort_sat.cl +++ b/libclc/test/binding/core/SConvert_Rshort_sat.cl @@ -20,27 +20,12 @@ test___spirv_SConvert_Rshort_sat(__clc_int8_t args_0) { return __spirv_SConvert_Rshort_sat(args_0); } -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort_sat(__clc_uint8_t args_0) { - return __spirv_SConvert_Rshort_sat(args_0); -} - __attribute__((overloadable)) __clc_int16_t test___spirv_SConvert_Rshort_sat(__clc_int32_t args_0) { return __spirv_SConvert_Rshort_sat(args_0); } -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort_sat(__clc_uint32_t args_0) { - return __spirv_SConvert_Rshort_sat(args_0); -} - __attribute__((overloadable)) __clc_int16_t test___spirv_SConvert_Rshort_sat(__clc_int64_t args_0) { return __spirv_SConvert_Rshort_sat(args_0); } - -__attribute__((overloadable)) __clc_int16_t -test___spirv_SConvert_Rshort_sat(__clc_uint64_t args_0) { - return __spirv_SConvert_Rshort_sat(args_0); -} diff --git a/libclc/test/binding/core/UConvert_Ruchar.cl b/libclc/test/binding/core/UConvert_Ruchar.cl index 30a94e7c307ed..6afde55c5b815 100644 --- a/libclc/test/binding/core/UConvert_Ruchar.cl +++ b/libclc/test/binding/core/UConvert_Ruchar.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar(__clc_int16_t args_0) { - return __spirv_UConvert_Ruchar(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar(__clc_uint16_t args_0) { return __spirv_UConvert_Ruchar(args_0); } -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar(__clc_int32_t args_0) { - return __spirv_UConvert_Ruchar(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar(__clc_uint32_t args_0) { return __spirv_UConvert_Ruchar(args_0); } -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar(__clc_int64_t args_0) { - return __spirv_UConvert_Ruchar(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar(__clc_uint64_t args_0) { return __spirv_UConvert_Ruchar(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar16.cl b/libclc/test/binding/core/UConvert_Ruchar16.cl index 45c64b762b96c..26270fb564a68 100644 --- a/libclc/test/binding/core/UConvert_Ruchar16.cl +++ b/libclc/test/binding/core/UConvert_Ruchar16.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Ruchar16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Ruchar16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Ruchar16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Ruchar16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Ruchar16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Ruchar16(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar16_sat.cl b/libclc/test/binding/core/UConvert_Ruchar16_sat.cl index 421102a4e3ab7..9d75bb414e124 100644 --- a/libclc/test/binding/core/UConvert_Ruchar16_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar16_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Ruchar16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Ruchar16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Ruchar16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Ruchar16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint8_t -test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Ruchar16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint8_t test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Ruchar16_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar2.cl b/libclc/test/binding/core/UConvert_Ruchar2.cl index 9b6804c51a4aa..e68867addd14b 100644 --- a/libclc/test/binding/core/UConvert_Ruchar2.cl +++ b/libclc/test/binding/core/UConvert_Ruchar2.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Ruchar2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Ruchar2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Ruchar2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Ruchar2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Ruchar2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Ruchar2(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar2_sat.cl b/libclc/test/binding/core/UConvert_Ruchar2_sat.cl index 30130495b4c8a..5d19324bc0660 100644 --- a/libclc/test/binding/core/UConvert_Ruchar2_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar2_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Ruchar2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Ruchar2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Ruchar2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Ruchar2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint8_t -test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Ruchar2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint8_t test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Ruchar2_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar3.cl b/libclc/test/binding/core/UConvert_Ruchar3.cl index 69e709b8397b3..0f9e8e08890f6 100644 --- a/libclc/test/binding/core/UConvert_Ruchar3.cl +++ b/libclc/test/binding/core/UConvert_Ruchar3.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Ruchar3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Ruchar3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Ruchar3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Ruchar3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Ruchar3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Ruchar3(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar3_sat.cl b/libclc/test/binding/core/UConvert_Ruchar3_sat.cl index 1479a08925cad..24b47feea3b64 100644 --- a/libclc/test/binding/core/UConvert_Ruchar3_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar3_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Ruchar3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Ruchar3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Ruchar3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Ruchar3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint8_t -test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Ruchar3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint8_t test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Ruchar3_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar4.cl b/libclc/test/binding/core/UConvert_Ruchar4.cl index b0c6dcd1c4e57..4e007caaaa598 100644 --- a/libclc/test/binding/core/UConvert_Ruchar4.cl +++ b/libclc/test/binding/core/UConvert_Ruchar4.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Ruchar4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Ruchar4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Ruchar4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Ruchar4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Ruchar4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Ruchar4(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar4_sat.cl b/libclc/test/binding/core/UConvert_Ruchar4_sat.cl index 569e9bb17f109..4b2fb67764ade 100644 --- a/libclc/test/binding/core/UConvert_Ruchar4_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar4_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Ruchar4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Ruchar4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Ruchar4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Ruchar4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint8_t -test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Ruchar4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint8_t test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Ruchar4_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar8.cl b/libclc/test/binding/core/UConvert_Ruchar8.cl index 1dabf0d1d69ef..f0275132b6ad3 100644 --- a/libclc/test/binding/core/UConvert_Ruchar8.cl +++ b/libclc/test/binding/core/UConvert_Ruchar8.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Ruchar8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Ruchar8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Ruchar8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Ruchar8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Ruchar8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Ruchar8(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar8_sat.cl b/libclc/test/binding/core/UConvert_Ruchar8_sat.cl index 029b4a446354a..1a6235c8a79ed 100644 --- a/libclc/test/binding/core/UConvert_Ruchar8_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar8_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Ruchar8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Ruchar8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Ruchar8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Ruchar8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint8_t -test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Ruchar8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint8_t test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Ruchar8_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruchar_sat.cl b/libclc/test/binding/core/UConvert_Ruchar_sat.cl index 90496d6631ca6..e8bf919b2a94f 100644 --- a/libclc/test/binding/core/UConvert_Ruchar_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruchar_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar_sat(__clc_int16_t args_0) { - return __spirv_UConvert_Ruchar_sat(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar_sat(__clc_uint16_t args_0) { return __spirv_UConvert_Ruchar_sat(args_0); } -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar_sat(__clc_int32_t args_0) { - return __spirv_UConvert_Ruchar_sat(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar_sat(__clc_uint32_t args_0) { return __spirv_UConvert_Ruchar_sat(args_0); } -__attribute__((overloadable)) __clc_uint8_t -test___spirv_UConvert_Ruchar_sat(__clc_int64_t args_0) { - return __spirv_UConvert_Ruchar_sat(args_0); -} - __attribute__((overloadable)) __clc_uint8_t test___spirv_UConvert_Ruchar_sat(__clc_uint64_t args_0) { return __spirv_UConvert_Ruchar_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint.cl b/libclc/test/binding/core/UConvert_Ruint.cl index 4634e45775ee1..426528a6bfabc 100644 --- a/libclc/test/binding/core/UConvert_Ruint.cl +++ b/libclc/test/binding/core/UConvert_Ruint.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint(__clc_int8_t args_0) { - return __spirv_UConvert_Ruint(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint(__clc_uint8_t args_0) { return __spirv_UConvert_Ruint(args_0); } -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint(__clc_int16_t args_0) { - return __spirv_UConvert_Ruint(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint(__clc_uint16_t args_0) { return __spirv_UConvert_Ruint(args_0); } -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint(__clc_int64_t args_0) { - return __spirv_UConvert_Ruint(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint(__clc_uint64_t args_0) { return __spirv_UConvert_Ruint(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint16.cl b/libclc/test/binding/core/UConvert_Ruint16.cl index 1b64ed77ad9e1..4a26348cba0a2 100644 --- a/libclc/test/binding/core/UConvert_Ruint16.cl +++ b/libclc/test/binding/core/UConvert_Ruint16.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Ruint16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Ruint16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Ruint16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Ruint16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Ruint16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Ruint16(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint16_sat.cl b/libclc/test/binding/core/UConvert_Ruint16_sat.cl index caf32fe57d1af..e726cf4a149a0 100644 --- a/libclc/test/binding/core/UConvert_Ruint16_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint16_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16_sat(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Ruint16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Ruint16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16_sat(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Ruint16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Ruint16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint32_t -test___spirv_UConvert_Ruint16_sat(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Ruint16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint32_t test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Ruint16_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint2.cl b/libclc/test/binding/core/UConvert_Ruint2.cl index 948755ca4d71a..9c1a878886ed9 100644 --- a/libclc/test/binding/core/UConvert_Ruint2.cl +++ b/libclc/test/binding/core/UConvert_Ruint2.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Ruint2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Ruint2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Ruint2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Ruint2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Ruint2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Ruint2(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint2_sat.cl b/libclc/test/binding/core/UConvert_Ruint2_sat.cl index 8acdbc81c8dd0..94154d523ad8f 100644 --- a/libclc/test/binding/core/UConvert_Ruint2_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint2_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2_sat(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Ruint2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Ruint2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2_sat(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Ruint2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Ruint2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint32_t -test___spirv_UConvert_Ruint2_sat(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Ruint2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint32_t test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Ruint2_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint3.cl b/libclc/test/binding/core/UConvert_Ruint3.cl index c640d35a5b41b..409d364105fb8 100644 --- a/libclc/test/binding/core/UConvert_Ruint3.cl +++ b/libclc/test/binding/core/UConvert_Ruint3.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Ruint3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Ruint3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Ruint3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Ruint3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Ruint3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Ruint3(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint3_sat.cl b/libclc/test/binding/core/UConvert_Ruint3_sat.cl index 954ee258d3fcd..2fb2964672359 100644 --- a/libclc/test/binding/core/UConvert_Ruint3_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint3_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3_sat(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Ruint3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Ruint3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3_sat(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Ruint3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Ruint3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint32_t -test___spirv_UConvert_Ruint3_sat(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Ruint3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint32_t test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Ruint3_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint4.cl b/libclc/test/binding/core/UConvert_Ruint4.cl index 1230800b6b501..2ed5c33fb491b 100644 --- a/libclc/test/binding/core/UConvert_Ruint4.cl +++ b/libclc/test/binding/core/UConvert_Ruint4.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Ruint4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Ruint4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Ruint4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Ruint4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Ruint4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Ruint4(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint4_sat.cl b/libclc/test/binding/core/UConvert_Ruint4_sat.cl index f2a19d2f0fedc..5fd5f41934b7e 100644 --- a/libclc/test/binding/core/UConvert_Ruint4_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint4_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4_sat(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Ruint4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Ruint4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4_sat(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Ruint4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Ruint4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint32_t -test___spirv_UConvert_Ruint4_sat(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Ruint4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint32_t test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Ruint4_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint8.cl b/libclc/test/binding/core/UConvert_Ruint8.cl index 66dddf6bf761c..4eb746b3a8cc8 100644 --- a/libclc/test/binding/core/UConvert_Ruint8.cl +++ b/libclc/test/binding/core/UConvert_Ruint8.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Ruint8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Ruint8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Ruint8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Ruint8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Ruint8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Ruint8(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint8_sat.cl b/libclc/test/binding/core/UConvert_Ruint8_sat.cl index 207c50a240ada..eed7aa854f52c 100644 --- a/libclc/test/binding/core/UConvert_Ruint8_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint8_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8_sat(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Ruint8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Ruint8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8_sat(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Ruint8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Ruint8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint32_t -test___spirv_UConvert_Ruint8_sat(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Ruint8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint32_t test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Ruint8_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Ruint_sat.cl b/libclc/test/binding/core/UConvert_Ruint_sat.cl index a74a6459fd3fc..3529f5920e26e 100644 --- a/libclc/test/binding/core/UConvert_Ruint_sat.cl +++ b/libclc/test/binding/core/UConvert_Ruint_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint_sat(__clc_int8_t args_0) { - return __spirv_UConvert_Ruint_sat(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint_sat(__clc_uint8_t args_0) { return __spirv_UConvert_Ruint_sat(args_0); } -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint_sat(__clc_int16_t args_0) { - return __spirv_UConvert_Ruint_sat(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint_sat(__clc_uint16_t args_0) { return __spirv_UConvert_Ruint_sat(args_0); } -__attribute__((overloadable)) __clc_uint32_t -test___spirv_UConvert_Ruint_sat(__clc_int64_t args_0) { - return __spirv_UConvert_Ruint_sat(args_0); -} - __attribute__((overloadable)) __clc_uint32_t test___spirv_UConvert_Ruint_sat(__clc_uint64_t args_0) { return __spirv_UConvert_Ruint_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong.cl b/libclc/test/binding/core/UConvert_Rulong.cl index ee1042730db46..8c826ff9ab705 100644 --- a/libclc/test/binding/core/UConvert_Rulong.cl +++ b/libclc/test/binding/core/UConvert_Rulong.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong(__clc_int8_t args_0) { - return __spirv_UConvert_Rulong(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong(__clc_uint8_t args_0) { return __spirv_UConvert_Rulong(args_0); } -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong(__clc_int16_t args_0) { - return __spirv_UConvert_Rulong(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong(__clc_uint16_t args_0) { return __spirv_UConvert_Rulong(args_0); } -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong(__clc_int32_t args_0) { - return __spirv_UConvert_Rulong(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong(__clc_uint32_t args_0) { return __spirv_UConvert_Rulong(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong16.cl b/libclc/test/binding/core/UConvert_Rulong16.cl index 4be1301a1d7dd..8d9cc7a30a24b 100644 --- a/libclc/test/binding/core/UConvert_Rulong16.cl +++ b/libclc/test/binding/core/UConvert_Rulong16.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Rulong16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Rulong16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Rulong16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Rulong16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Rulong16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Rulong16(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong16_sat.cl b/libclc/test/binding/core/UConvert_Rulong16_sat.cl index e52d225583c2b..102cc614b66b8 100644 --- a/libclc/test/binding/core/UConvert_Rulong16_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong16_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16_sat(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Rulong16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Rulong16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16_sat(__clc_vec16_int16_t args_0) { - return __spirv_UConvert_Rulong16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint16_t args_0) { return __spirv_UConvert_Rulong16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint64_t -test___spirv_UConvert_Rulong16_sat(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Rulong16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint64_t test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Rulong16_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong2.cl b/libclc/test/binding/core/UConvert_Rulong2.cl index 6e01ec0a3b880..92d6a8688bbda 100644 --- a/libclc/test/binding/core/UConvert_Rulong2.cl +++ b/libclc/test/binding/core/UConvert_Rulong2.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Rulong2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Rulong2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Rulong2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Rulong2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Rulong2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Rulong2(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong2_sat.cl b/libclc/test/binding/core/UConvert_Rulong2_sat.cl index 1a94f48d63168..746b20c8de502 100644 --- a/libclc/test/binding/core/UConvert_Rulong2_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong2_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2_sat(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Rulong2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Rulong2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2_sat(__clc_vec2_int16_t args_0) { - return __spirv_UConvert_Rulong2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint16_t args_0) { return __spirv_UConvert_Rulong2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint64_t -test___spirv_UConvert_Rulong2_sat(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Rulong2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint64_t test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Rulong2_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong3.cl b/libclc/test/binding/core/UConvert_Rulong3.cl index e462276686edf..7f30f21f1adfa 100644 --- a/libclc/test/binding/core/UConvert_Rulong3.cl +++ b/libclc/test/binding/core/UConvert_Rulong3.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Rulong3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Rulong3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Rulong3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Rulong3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Rulong3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Rulong3(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong3_sat.cl b/libclc/test/binding/core/UConvert_Rulong3_sat.cl index 53d013b44ad1c..c8bc886be8cff 100644 --- a/libclc/test/binding/core/UConvert_Rulong3_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong3_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3_sat(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Rulong3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Rulong3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3_sat(__clc_vec3_int16_t args_0) { - return __spirv_UConvert_Rulong3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint16_t args_0) { return __spirv_UConvert_Rulong3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint64_t -test___spirv_UConvert_Rulong3_sat(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Rulong3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint64_t test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Rulong3_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong4.cl b/libclc/test/binding/core/UConvert_Rulong4.cl index fdd4e4540a4be..902373c809589 100644 --- a/libclc/test/binding/core/UConvert_Rulong4.cl +++ b/libclc/test/binding/core/UConvert_Rulong4.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Rulong4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Rulong4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Rulong4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Rulong4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Rulong4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Rulong4(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong4_sat.cl b/libclc/test/binding/core/UConvert_Rulong4_sat.cl index cb6a04f6359bb..7543f1a92458e 100644 --- a/libclc/test/binding/core/UConvert_Rulong4_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong4_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4_sat(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Rulong4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Rulong4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4_sat(__clc_vec4_int16_t args_0) { - return __spirv_UConvert_Rulong4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint16_t args_0) { return __spirv_UConvert_Rulong4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint64_t -test___spirv_UConvert_Rulong4_sat(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Rulong4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint64_t test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Rulong4_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong8.cl b/libclc/test/binding/core/UConvert_Rulong8.cl index 1c0c902cbbb52..dd43bfda24b20 100644 --- a/libclc/test/binding/core/UConvert_Rulong8.cl +++ b/libclc/test/binding/core/UConvert_Rulong8.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Rulong8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Rulong8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Rulong8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Rulong8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Rulong8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Rulong8(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong8_sat.cl b/libclc/test/binding/core/UConvert_Rulong8_sat.cl index c050aebb4623a..15f72bc393d1c 100644 --- a/libclc/test/binding/core/UConvert_Rulong8_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong8_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8_sat(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Rulong8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Rulong8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8_sat(__clc_vec8_int16_t args_0) { - return __spirv_UConvert_Rulong8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint16_t args_0) { return __spirv_UConvert_Rulong8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint64_t -test___spirv_UConvert_Rulong8_sat(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Rulong8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint64_t test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Rulong8_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rulong_sat.cl b/libclc/test/binding/core/UConvert_Rulong_sat.cl index 8ba6e9e6f8d6a..d1561646ba385 100644 --- a/libclc/test/binding/core/UConvert_Rulong_sat.cl +++ b/libclc/test/binding/core/UConvert_Rulong_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong_sat(__clc_int8_t args_0) { - return __spirv_UConvert_Rulong_sat(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong_sat(__clc_uint8_t args_0) { return __spirv_UConvert_Rulong_sat(args_0); } -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong_sat(__clc_int16_t args_0) { - return __spirv_UConvert_Rulong_sat(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong_sat(__clc_uint16_t args_0) { return __spirv_UConvert_Rulong_sat(args_0); } -__attribute__((overloadable)) __clc_uint64_t -test___spirv_UConvert_Rulong_sat(__clc_int32_t args_0) { - return __spirv_UConvert_Rulong_sat(args_0); -} - __attribute__((overloadable)) __clc_uint64_t test___spirv_UConvert_Rulong_sat(__clc_uint32_t args_0) { return __spirv_UConvert_Rulong_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort.cl b/libclc/test/binding/core/UConvert_Rushort.cl index c16db1c7e2628..84a9eb76afcf5 100644 --- a/libclc/test/binding/core/UConvert_Rushort.cl +++ b/libclc/test/binding/core/UConvert_Rushort.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort(__clc_int8_t args_0) { - return __spirv_UConvert_Rushort(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort(__clc_uint8_t args_0) { return __spirv_UConvert_Rushort(args_0); } -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort(__clc_int32_t args_0) { - return __spirv_UConvert_Rushort(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort(__clc_uint32_t args_0) { return __spirv_UConvert_Rushort(args_0); } -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort(__clc_int64_t args_0) { - return __spirv_UConvert_Rushort(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort(__clc_uint64_t args_0) { return __spirv_UConvert_Rushort(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort16.cl b/libclc/test/binding/core/UConvert_Rushort16.cl index 518de0bde7c6c..e97f252a3b125 100644 --- a/libclc/test/binding/core/UConvert_Rushort16.cl +++ b/libclc/test/binding/core/UConvert_Rushort16.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Rushort16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Rushort16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Rushort16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Rushort16(args_0); } -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Rushort16(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Rushort16(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort16_sat.cl b/libclc/test/binding/core/UConvert_Rushort16_sat.cl index 0f0ac5676fb2c..9c3f804724247 100644 --- a/libclc/test/binding/core/UConvert_Rushort16_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort16_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16_sat(__clc_vec16_int8_t args_0) { - return __spirv_UConvert_Rushort16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint8_t args_0) { return __spirv_UConvert_Rushort16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16_sat(__clc_vec16_int32_t args_0) { - return __spirv_UConvert_Rushort16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint32_t args_0) { return __spirv_UConvert_Rushort16_sat(args_0); } -__attribute__((overloadable)) __clc_vec16_uint16_t -test___spirv_UConvert_Rushort16_sat(__clc_vec16_int64_t args_0) { - return __spirv_UConvert_Rushort16_sat(args_0); -} - __attribute__((overloadable)) __clc_vec16_uint16_t test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint64_t args_0) { return __spirv_UConvert_Rushort16_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort2.cl b/libclc/test/binding/core/UConvert_Rushort2.cl index 410fc82b6c8d9..e4b3b0b7c7ac6 100644 --- a/libclc/test/binding/core/UConvert_Rushort2.cl +++ b/libclc/test/binding/core/UConvert_Rushort2.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Rushort2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Rushort2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Rushort2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Rushort2(args_0); } -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Rushort2(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Rushort2(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort2_sat.cl b/libclc/test/binding/core/UConvert_Rushort2_sat.cl index 780e3bfa551f8..50e9e54b3daa7 100644 --- a/libclc/test/binding/core/UConvert_Rushort2_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort2_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2_sat(__clc_vec2_int8_t args_0) { - return __spirv_UConvert_Rushort2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint8_t args_0) { return __spirv_UConvert_Rushort2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2_sat(__clc_vec2_int32_t args_0) { - return __spirv_UConvert_Rushort2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint32_t args_0) { return __spirv_UConvert_Rushort2_sat(args_0); } -__attribute__((overloadable)) __clc_vec2_uint16_t -test___spirv_UConvert_Rushort2_sat(__clc_vec2_int64_t args_0) { - return __spirv_UConvert_Rushort2_sat(args_0); -} - __attribute__((overloadable)) __clc_vec2_uint16_t test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint64_t args_0) { return __spirv_UConvert_Rushort2_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort3.cl b/libclc/test/binding/core/UConvert_Rushort3.cl index 1580b15f09e04..9a21942a349a6 100644 --- a/libclc/test/binding/core/UConvert_Rushort3.cl +++ b/libclc/test/binding/core/UConvert_Rushort3.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Rushort3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Rushort3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Rushort3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Rushort3(args_0); } -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Rushort3(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Rushort3(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort3_sat.cl b/libclc/test/binding/core/UConvert_Rushort3_sat.cl index 8ad31b327f000..c96826c3bf19d 100644 --- a/libclc/test/binding/core/UConvert_Rushort3_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort3_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3_sat(__clc_vec3_int8_t args_0) { - return __spirv_UConvert_Rushort3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint8_t args_0) { return __spirv_UConvert_Rushort3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3_sat(__clc_vec3_int32_t args_0) { - return __spirv_UConvert_Rushort3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint32_t args_0) { return __spirv_UConvert_Rushort3_sat(args_0); } -__attribute__((overloadable)) __clc_vec3_uint16_t -test___spirv_UConvert_Rushort3_sat(__clc_vec3_int64_t args_0) { - return __spirv_UConvert_Rushort3_sat(args_0); -} - __attribute__((overloadable)) __clc_vec3_uint16_t test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint64_t args_0) { return __spirv_UConvert_Rushort3_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort4.cl b/libclc/test/binding/core/UConvert_Rushort4.cl index 92d5d1779e8dd..56a31bbb2df73 100644 --- a/libclc/test/binding/core/UConvert_Rushort4.cl +++ b/libclc/test/binding/core/UConvert_Rushort4.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Rushort4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Rushort4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Rushort4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Rushort4(args_0); } -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Rushort4(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Rushort4(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort4_sat.cl b/libclc/test/binding/core/UConvert_Rushort4_sat.cl index 71bde2cb55756..8bfbc71ff4d75 100644 --- a/libclc/test/binding/core/UConvert_Rushort4_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort4_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4_sat(__clc_vec4_int8_t args_0) { - return __spirv_UConvert_Rushort4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint8_t args_0) { return __spirv_UConvert_Rushort4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4_sat(__clc_vec4_int32_t args_0) { - return __spirv_UConvert_Rushort4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint32_t args_0) { return __spirv_UConvert_Rushort4_sat(args_0); } -__attribute__((overloadable)) __clc_vec4_uint16_t -test___spirv_UConvert_Rushort4_sat(__clc_vec4_int64_t args_0) { - return __spirv_UConvert_Rushort4_sat(args_0); -} - __attribute__((overloadable)) __clc_vec4_uint16_t test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint64_t args_0) { return __spirv_UConvert_Rushort4_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort8.cl b/libclc/test/binding/core/UConvert_Rushort8.cl index f0b26c3c3b9cb..32790cbc2f334 100644 --- a/libclc/test/binding/core/UConvert_Rushort8.cl +++ b/libclc/test/binding/core/UConvert_Rushort8.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Rushort8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Rushort8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Rushort8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Rushort8(args_0); } -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Rushort8(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Rushort8(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort8_sat.cl b/libclc/test/binding/core/UConvert_Rushort8_sat.cl index 41ca4f238b784..ffe09255fbc1f 100644 --- a/libclc/test/binding/core/UConvert_Rushort8_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort8_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8_sat(__clc_vec8_int8_t args_0) { - return __spirv_UConvert_Rushort8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint8_t args_0) { return __spirv_UConvert_Rushort8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8_sat(__clc_vec8_int32_t args_0) { - return __spirv_UConvert_Rushort8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint32_t args_0) { return __spirv_UConvert_Rushort8_sat(args_0); } -__attribute__((overloadable)) __clc_vec8_uint16_t -test___spirv_UConvert_Rushort8_sat(__clc_vec8_int64_t args_0) { - return __spirv_UConvert_Rushort8_sat(args_0); -} - __attribute__((overloadable)) __clc_vec8_uint16_t test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint64_t args_0) { return __spirv_UConvert_Rushort8_sat(args_0); diff --git a/libclc/test/binding/core/UConvert_Rushort_sat.cl b/libclc/test/binding/core/UConvert_Rushort_sat.cl index 3b99ce023324c..da49cef805dea 100644 --- a/libclc/test/binding/core/UConvert_Rushort_sat.cl +++ b/libclc/test/binding/core/UConvert_Rushort_sat.cl @@ -15,31 +15,16 @@ // CHECK-NOT: declare {{.*}} @_Z // CHECK-NOT: call {{[^ ]*}} bitcast -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort_sat(__clc_int8_t args_0) { - return __spirv_UConvert_Rushort_sat(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort_sat(__clc_uint8_t args_0) { return __spirv_UConvert_Rushort_sat(args_0); } -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort_sat(__clc_int32_t args_0) { - return __spirv_UConvert_Rushort_sat(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort_sat(__clc_uint32_t args_0) { return __spirv_UConvert_Rushort_sat(args_0); } -__attribute__((overloadable)) __clc_uint16_t -test___spirv_UConvert_Rushort_sat(__clc_int64_t args_0) { - return __spirv_UConvert_Rushort_sat(args_0); -} - __attribute__((overloadable)) __clc_uint16_t test___spirv_UConvert_Rushort_sat(__clc_uint64_t args_0) { return __spirv_UConvert_Rushort_sat(args_0); diff --git a/libclc/test/binding/ocl/ldexp.cl b/libclc/test/binding/ocl/ldexp.cl index 6299913350603..a890f53a5c077 100644 --- a/libclc/test/binding/ocl/ldexp.cl +++ b/libclc/test/binding/ocl/ldexp.cl @@ -45,36 +45,6 @@ test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t args_1) { return __spirv_ocl_ldexp(args_0, args_1); } -__attribute__((overloadable)) __clc_fp32_t -test___spirv_ocl_ldexp(__clc_fp32_t args_0, __clc_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -__attribute__((overloadable)) __clc_vec2_fp32_t -test___spirv_ocl_ldexp(__clc_vec2_fp32_t args_0, __clc_vec2_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -__attribute__((overloadable)) __clc_vec3_fp32_t -test___spirv_ocl_ldexp(__clc_vec3_fp32_t args_0, __clc_vec3_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -__attribute__((overloadable)) __clc_vec4_fp32_t -test___spirv_ocl_ldexp(__clc_vec4_fp32_t args_0, __clc_vec4_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -__attribute__((overloadable)) __clc_vec8_fp32_t -test___spirv_ocl_ldexp(__clc_vec8_fp32_t args_0, __clc_vec8_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -__attribute__((overloadable)) __clc_vec16_fp32_t -test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - #ifdef cl_khr_fp64 __attribute__((overloadable)) __clc_fp64_t test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_int32_t args_1) { @@ -117,48 +87,7 @@ test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t args_1) { } #endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_fp64_t -test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_vec2_fp64_t -test___spirv_ocl_ldexp(__clc_vec2_fp64_t args_0, __clc_vec2_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_vec3_fp64_t -test___spirv_ocl_ldexp(__clc_vec3_fp64_t args_0, __clc_vec3_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_vec4_fp64_t -test___spirv_ocl_ldexp(__clc_vec4_fp64_t args_0, __clc_vec4_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} -#endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_vec8_fp64_t -test___spirv_ocl_ldexp(__clc_vec8_fp64_t args_0, __clc_vec8_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp64 -__attribute__((overloadable)) __clc_vec16_fp64_t -test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif #ifdef cl_khr_fp16 __attribute__((overloadable)) __clc_fp16_t test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_int32_t args_1) { @@ -201,45 +130,3 @@ test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t args_1) { } #endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_fp16_t -test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_vec2_fp16_t -test___spirv_ocl_ldexp(__clc_vec2_fp16_t args_0, __clc_vec2_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_vec3_fp16_t -test___spirv_ocl_ldexp(__clc_vec3_fp16_t args_0, __clc_vec3_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_vec4_fp16_t -test___spirv_ocl_ldexp(__clc_vec4_fp16_t args_0, __clc_vec4_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_vec8_fp16_t -test___spirv_ocl_ldexp(__clc_vec8_fp16_t args_0, __clc_vec8_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif -#ifdef cl_khr_fp16 -__attribute__((overloadable)) __clc_vec16_fp16_t -test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_uint32_t args_1) { - return __spirv_ocl_ldexp(args_0, args_1); -} - -#endif diff --git a/libclc/test/binding/ocl/vload_half.cl b/libclc/test/binding/ocl/vload_half.cl index 396177ecbb9c0..e516be552ba8e 100644 --- a/libclc/test/binding/ocl/vload_half.cl +++ b/libclc/test/binding/ocl/vload_half.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl index d10cb72ac990d..cef1c5bc3118b 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl index 2dfcf883766ab..669ae0592138a 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl index 37cf66c296752..fa9a50641741f 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl index d141b6fc37b12..e84ee7f50ffc6 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl index 628ba269f91e3..085194dfc3c09 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl index a6cb6fb2daac0..9d8d667f94c50 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl index 2fcf239da4abf..15b32c3c2b6e1 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl index f4af130a284a3..762f49be0fe2c 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl index c4037d16946bd..a6a9d9fe834ff 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl index 5704c6fe5680c..91bc4440dc102 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar16.cl b/libclc/test/binding/ocl/vloadn_Rchar16.cl index cc6ddd06345e5..fb5af1fa9591c 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar16.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar2.cl b/libclc/test/binding/ocl/vloadn_Rchar2.cl index 4ba2b9bd1b38b..2b5a6860a64a1 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar2.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar3.cl b/libclc/test/binding/ocl/vloadn_Rchar3.cl index b4019a2820c22..2791ab586c54b 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar3.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar4.cl b/libclc/test/binding/ocl/vloadn_Rchar4.cl index ef3fa77c56a09..1af4797e085c3 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar4.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar8.cl b/libclc/test/binding/ocl/vloadn_Rchar8.cl index e03c072e42f4d..e4a69a5e5887d 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar8.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble16.cl b/libclc/test/binding/ocl/vloadn_Rdouble16.cl index 1baa75932f69f..76a04be4f9800 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble16.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble2.cl b/libclc/test/binding/ocl/vloadn_Rdouble2.cl index a78175c858f5d..29c92af58c145 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble2.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble3.cl b/libclc/test/binding/ocl/vloadn_Rdouble3.cl index 7e6f67cf6aba7..047d5d23234be 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble3.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble4.cl b/libclc/test/binding/ocl/vloadn_Rdouble4.cl index 6c9199efc7501..0b164112c073f 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble4.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble8.cl b/libclc/test/binding/ocl/vloadn_Rdouble8.cl index fab3d6470e59e..11f6bfbc704f1 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble8.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat16.cl b/libclc/test/binding/ocl/vloadn_Rfloat16.cl index 0a9ccbca49ad8..ebf8c4bbd088e 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat2.cl b/libclc/test/binding/ocl/vloadn_Rfloat2.cl index 1a2a7fce96ce3..64758fb4c28c6 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat3.cl b/libclc/test/binding/ocl/vloadn_Rfloat3.cl index 8d37f39867ed5..8b5546e213702 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat4.cl b/libclc/test/binding/ocl/vloadn_Rfloat4.cl index 8ba449cf63d1d..abde3e79bc12c 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat8.cl b/libclc/test/binding/ocl/vloadn_Rfloat8.cl index 35d19138b7467..15c12d8db5e30 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf16.cl b/libclc/test/binding/ocl/vloadn_Rhalf16.cl index 13fbe403451fc..2a0b1f0733d2c 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf16.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf2.cl b/libclc/test/binding/ocl/vloadn_Rhalf2.cl index 38b232c37ae4a..ef88cea6484f4 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf2.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf3.cl b/libclc/test/binding/ocl/vloadn_Rhalf3.cl index de1914637a370..98410f7d3717b 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf3.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf4.cl b/libclc/test/binding/ocl/vloadn_Rhalf4.cl index dd67ec602c3a8..01137ec288043 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf4.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf8.cl b/libclc/test/binding/ocl/vloadn_Rhalf8.cl index c779ea5e87859..968245b390a5e 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf8.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint16.cl b/libclc/test/binding/ocl/vloadn_Rint16.cl index d141ab36f8884..4998a0e076f9c 100644 --- a/libclc/test/binding/ocl/vloadn_Rint16.cl +++ b/libclc/test/binding/ocl/vloadn_Rint16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint2.cl b/libclc/test/binding/ocl/vloadn_Rint2.cl index e768bc11e7d51..2bd32a407acd9 100644 --- a/libclc/test/binding/ocl/vloadn_Rint2.cl +++ b/libclc/test/binding/ocl/vloadn_Rint2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint3.cl b/libclc/test/binding/ocl/vloadn_Rint3.cl index 2ddab761c9237..f5c4923df9bd7 100644 --- a/libclc/test/binding/ocl/vloadn_Rint3.cl +++ b/libclc/test/binding/ocl/vloadn_Rint3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint4.cl b/libclc/test/binding/ocl/vloadn_Rint4.cl index f672444b2468e..b73c72baa235d 100644 --- a/libclc/test/binding/ocl/vloadn_Rint4.cl +++ b/libclc/test/binding/ocl/vloadn_Rint4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint8.cl b/libclc/test/binding/ocl/vloadn_Rint8.cl index 27237ec1bae1a..07c69240f82d9 100644 --- a/libclc/test/binding/ocl/vloadn_Rint8.cl +++ b/libclc/test/binding/ocl/vloadn_Rint8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong16.cl b/libclc/test/binding/ocl/vloadn_Rlong16.cl index 455a4907e0b14..9baf2727c4501 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong16.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong2.cl b/libclc/test/binding/ocl/vloadn_Rlong2.cl index b64065e48804f..35a105b86783c 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong2.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong3.cl b/libclc/test/binding/ocl/vloadn_Rlong3.cl index 207ee7fe79543..75b53b2afea41 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong3.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong4.cl b/libclc/test/binding/ocl/vloadn_Rlong4.cl index ca48f124f261e..6594a6ee17382 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong4.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong8.cl b/libclc/test/binding/ocl/vloadn_Rlong8.cl index 795bd3d446e3d..fe45150d1e3db 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong8.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort16.cl b/libclc/test/binding/ocl/vloadn_Rshort16.cl index ad74ee6029399..9a45d640ba069 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort16.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort2.cl b/libclc/test/binding/ocl/vloadn_Rshort2.cl index 02e0f086e0ad0..9ff4871a03040 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort2.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort3.cl b/libclc/test/binding/ocl/vloadn_Rshort3.cl index 32b3b8726cf6c..6a0852126d29c 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort3.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort4.cl b/libclc/test/binding/ocl/vloadn_Rshort4.cl index 5fcffd552dd60..2c0f6be25256c 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort4.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort8.cl b/libclc/test/binding/ocl/vloadn_Rshort8.cl index 84d1747965158..2eeb3d1aee1d3 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort8.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar16.cl b/libclc/test/binding/ocl/vloadn_Ruchar16.cl index 1aebe0191d430..66342ea644f41 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar16.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar2.cl b/libclc/test/binding/ocl/vloadn_Ruchar2.cl index 4e0f94da81b42..f4bf238100240 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar2.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar3.cl b/libclc/test/binding/ocl/vloadn_Ruchar3.cl index 8326ada0462ca..b26bdd90be104 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar3.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar4.cl b/libclc/test/binding/ocl/vloadn_Ruchar4.cl index f2df4aa28abd5..c640093108f41 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar4.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar8.cl b/libclc/test/binding/ocl/vloadn_Ruchar8.cl index 08c2d2295b4cc..ecef71abba3d4 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar8.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint16.cl b/libclc/test/binding/ocl/vloadn_Ruint16.cl index 9105f7979bc23..d49325ce1bb16 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint16.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint2.cl b/libclc/test/binding/ocl/vloadn_Ruint2.cl index bbe03b141059c..dfc911889818a 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint2.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint3.cl b/libclc/test/binding/ocl/vloadn_Ruint3.cl index bcd6f8b1be7bd..78acd15f09625 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint3.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint4.cl b/libclc/test/binding/ocl/vloadn_Ruint4.cl index 4870b943d1ee7..643ab6253bdba 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint4.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint8.cl b/libclc/test/binding/ocl/vloadn_Ruint8.cl index 147996de2fd77..74a01e7b46aa8 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint8.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong16.cl b/libclc/test/binding/ocl/vloadn_Rulong16.cl index c590cb1e1f173..145b972f2a548 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong16.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong2.cl b/libclc/test/binding/ocl/vloadn_Rulong2.cl index ce62abf499fdd..e088b8246ca92 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong2.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong3.cl b/libclc/test/binding/ocl/vloadn_Rulong3.cl index 619b38d77649a..3f9fa389bfaac 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong3.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong4.cl b/libclc/test/binding/ocl/vloadn_Rulong4.cl index cb5adb70a9df6..b7487e9e49316 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong4.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong8.cl b/libclc/test/binding/ocl/vloadn_Rulong8.cl index cdccea298787b..58a4edcc23c0f 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong8.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort16.cl b/libclc/test/binding/ocl/vloadn_Rushort16.cl index dd1d7c8214c45..c050147b0833f 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort16.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort16.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort2.cl b/libclc/test/binding/ocl/vloadn_Rushort2.cl index 795b3078cae9b..6cf667b230739 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort2.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort2.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort3.cl b/libclc/test/binding/ocl/vloadn_Rushort3.cl index a0c37eccf4411..242c407988d35 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort3.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort3.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort4.cl b/libclc/test/binding/ocl/vloadn_Rushort4.cl index b69edb7ec1932..76825ee509ad1 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort4.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort4.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort8.cl b/libclc/test/binding/ocl/vloadn_Rushort8.cl index 381199d732a80..a54af575254ba 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort8.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort8.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_half.cl b/libclc/test/binding/ocl/vstore_half.cl index 2e601e7f39d14..d47f6950be020 100644 --- a/libclc/test/binding/ocl/vstore_half.cl +++ b/libclc/test/binding/ocl/vstore_half.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_half_r.cl b/libclc/test/binding/ocl/vstore_half_r.cl index 370b470fc4c3b..f1d0157984d68 100644 --- a/libclc/test/binding/ocl/vstore_half_r.cl +++ b/libclc/test/binding/ocl/vstore_half_r.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_halfn.cl b/libclc/test/binding/ocl/vstore_halfn.cl index 4285fa20c6428..c87f071383ffa 100644 --- a/libclc/test/binding/ocl/vstore_halfn.cl +++ b/libclc/test/binding/ocl/vstore_halfn.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_halfn_r.cl b/libclc/test/binding/ocl/vstore_halfn_r.cl index 7cf8a23946bdb..7bcdeefae0069 100644 --- a/libclc/test/binding/ocl/vstore_halfn_r.cl +++ b/libclc/test/binding/ocl/vstore_halfn_r.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstorea_halfn.cl b/libclc/test/binding/ocl/vstorea_halfn.cl index 0152b798e9902..9b4d366d661ad 100644 --- a/libclc/test/binding/ocl/vstorea_halfn.cl +++ b/libclc/test/binding/ocl/vstorea_halfn.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstorea_halfn_r.cl b/libclc/test/binding/ocl/vstorea_halfn_r.cl index 65e2eee261d76..915c40f532c49 100644 --- a/libclc/test/binding/ocl/vstorea_halfn_r.cl +++ b/libclc/test/binding/ocl/vstorea_halfn_r.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstoren.cl b/libclc/test/binding/ocl/vstoren.cl index 40e43ca01d7be..106275b8b64a5 100644 --- a/libclc/test/binding/ocl/vstoren.cl +++ b/libclc/test/binding/ocl/vstoren.cl @@ -9,6 +9,12 @@ // Autogenerated by gen-libclc-test.py +// INTEL_CUSTOMIZATION +// Mark as unsupported until built-in signature is consistent between libspirv and +// SPV-IR of SPIRV-LLVM-Translator. +// UNSUPPORTED: true +// end INTEL_CUSTOMIZATION + // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include From 48d8f1cdcbd95335c1a4041fa7bcd53bb5ec1a8f Mon Sep 17 00:00:00 2001 From: Wenju He Date: Mon, 7 Jul 2025 06:11:05 +0200 Subject: [PATCH 2/4] revert irrelevant changes to ldexp, vload and vstore --- libclc/test/binding/ocl/ldexp.cl | 113 ++++++++++++++++++ libclc/test/binding/ocl/vload_half.cl | 6 - .../test/binding/ocl/vload_halfn_Rfloat16.cl | 6 - .../test/binding/ocl/vload_halfn_Rfloat2.cl | 6 - .../test/binding/ocl/vload_halfn_Rfloat3.cl | 6 - .../test/binding/ocl/vload_halfn_Rfloat4.cl | 6 - .../test/binding/ocl/vload_halfn_Rfloat8.cl | 6 - .../test/binding/ocl/vloada_halfn_Rfloat16.cl | 6 - .../test/binding/ocl/vloada_halfn_Rfloat2.cl | 6 - .../test/binding/ocl/vloada_halfn_Rfloat3.cl | 6 - .../test/binding/ocl/vloada_halfn_Rfloat4.cl | 6 - .../test/binding/ocl/vloada_halfn_Rfloat8.cl | 6 - libclc/test/binding/ocl/vloadn_Rchar16.cl | 6 - libclc/test/binding/ocl/vloadn_Rchar2.cl | 6 - libclc/test/binding/ocl/vloadn_Rchar3.cl | 6 - libclc/test/binding/ocl/vloadn_Rchar4.cl | 6 - libclc/test/binding/ocl/vloadn_Rchar8.cl | 6 - libclc/test/binding/ocl/vloadn_Rdouble16.cl | 6 - libclc/test/binding/ocl/vloadn_Rdouble2.cl | 6 - libclc/test/binding/ocl/vloadn_Rdouble3.cl | 6 - libclc/test/binding/ocl/vloadn_Rdouble4.cl | 6 - libclc/test/binding/ocl/vloadn_Rdouble8.cl | 6 - libclc/test/binding/ocl/vloadn_Rfloat16.cl | 6 - libclc/test/binding/ocl/vloadn_Rfloat2.cl | 6 - libclc/test/binding/ocl/vloadn_Rfloat3.cl | 6 - libclc/test/binding/ocl/vloadn_Rfloat4.cl | 6 - libclc/test/binding/ocl/vloadn_Rfloat8.cl | 6 - libclc/test/binding/ocl/vloadn_Rhalf16.cl | 6 - libclc/test/binding/ocl/vloadn_Rhalf2.cl | 6 - libclc/test/binding/ocl/vloadn_Rhalf3.cl | 6 - libclc/test/binding/ocl/vloadn_Rhalf4.cl | 6 - libclc/test/binding/ocl/vloadn_Rhalf8.cl | 6 - libclc/test/binding/ocl/vloadn_Rint16.cl | 6 - libclc/test/binding/ocl/vloadn_Rint2.cl | 6 - libclc/test/binding/ocl/vloadn_Rint3.cl | 6 - libclc/test/binding/ocl/vloadn_Rint4.cl | 6 - libclc/test/binding/ocl/vloadn_Rint8.cl | 6 - libclc/test/binding/ocl/vloadn_Rlong16.cl | 6 - libclc/test/binding/ocl/vloadn_Rlong2.cl | 6 - libclc/test/binding/ocl/vloadn_Rlong3.cl | 6 - libclc/test/binding/ocl/vloadn_Rlong4.cl | 6 - libclc/test/binding/ocl/vloadn_Rlong8.cl | 6 - libclc/test/binding/ocl/vloadn_Rshort16.cl | 6 - libclc/test/binding/ocl/vloadn_Rshort2.cl | 6 - libclc/test/binding/ocl/vloadn_Rshort3.cl | 6 - libclc/test/binding/ocl/vloadn_Rshort4.cl | 6 - libclc/test/binding/ocl/vloadn_Rshort8.cl | 6 - libclc/test/binding/ocl/vloadn_Ruchar16.cl | 6 - libclc/test/binding/ocl/vloadn_Ruchar2.cl | 6 - libclc/test/binding/ocl/vloadn_Ruchar3.cl | 6 - libclc/test/binding/ocl/vloadn_Ruchar4.cl | 6 - libclc/test/binding/ocl/vloadn_Ruchar8.cl | 6 - libclc/test/binding/ocl/vloadn_Ruint16.cl | 6 - libclc/test/binding/ocl/vloadn_Ruint2.cl | 6 - libclc/test/binding/ocl/vloadn_Ruint3.cl | 6 - libclc/test/binding/ocl/vloadn_Ruint4.cl | 6 - libclc/test/binding/ocl/vloadn_Ruint8.cl | 6 - libclc/test/binding/ocl/vloadn_Rulong16.cl | 6 - libclc/test/binding/ocl/vloadn_Rulong2.cl | 6 - libclc/test/binding/ocl/vloadn_Rulong3.cl | 6 - libclc/test/binding/ocl/vloadn_Rulong4.cl | 6 - libclc/test/binding/ocl/vloadn_Rulong8.cl | 6 - libclc/test/binding/ocl/vloadn_Rushort16.cl | 6 - libclc/test/binding/ocl/vloadn_Rushort2.cl | 6 - libclc/test/binding/ocl/vloadn_Rushort3.cl | 6 - libclc/test/binding/ocl/vloadn_Rushort4.cl | 6 - libclc/test/binding/ocl/vloadn_Rushort8.cl | 6 - libclc/test/binding/ocl/vstore_half.cl | 6 - libclc/test/binding/ocl/vstore_half_r.cl | 6 - libclc/test/binding/ocl/vstore_halfn.cl | 6 - libclc/test/binding/ocl/vstore_halfn_r.cl | 6 - libclc/test/binding/ocl/vstorea_halfn.cl | 6 - libclc/test/binding/ocl/vstorea_halfn_r.cl | 6 - libclc/test/binding/ocl/vstoren.cl | 6 - 74 files changed, 113 insertions(+), 438 deletions(-) diff --git a/libclc/test/binding/ocl/ldexp.cl b/libclc/test/binding/ocl/ldexp.cl index a890f53a5c077..6299913350603 100644 --- a/libclc/test/binding/ocl/ldexp.cl +++ b/libclc/test/binding/ocl/ldexp.cl @@ -45,6 +45,36 @@ test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t args_1) { return __spirv_ocl_ldexp(args_0, args_1); } +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_ldexp(__clc_fp32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_ldexp(__clc_vec2_fp32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_ldexp(__clc_vec3_fp32_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_ldexp(__clc_vec4_fp32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_ldexp(__clc_vec8_fp32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + #ifdef cl_khr_fp64 __attribute__((overloadable)) __clc_fp64_t test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_int32_t args_1) { @@ -87,7 +117,48 @@ test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t args_1) { } #endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_ldexp(__clc_vec2_fp64_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_ldexp(__clc_vec3_fp64_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_ldexp(__clc_vec4_fp64_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_ldexp(__clc_vec8_fp64_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif #ifdef cl_khr_fp16 __attribute__((overloadable)) __clc_fp16_t test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_int32_t args_1) { @@ -130,3 +201,45 @@ test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t args_1) { } #endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_ldexp(__clc_vec2_fp16_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_ldexp(__clc_vec3_fp16_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_ldexp(__clc_vec4_fp16_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_ldexp(__clc_vec8_fp16_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_half.cl b/libclc/test/binding/ocl/vload_half.cl index e516be552ba8e..396177ecbb9c0 100644 --- a/libclc/test/binding/ocl/vload_half.cl +++ b/libclc/test/binding/ocl/vload_half.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl index cef1c5bc3118b..d10cb72ac990d 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl index 669ae0592138a..2dfcf883766ab 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl index fa9a50641741f..37cf66c296752 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl index e84ee7f50ffc6..d141b6fc37b12 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl index 085194dfc3c09..628ba269f91e3 100644 --- a/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl index 9d8d667f94c50..a6cb6fb2daac0 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl index 15b32c3c2b6e1..2fcf239da4abf 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl index 762f49be0fe2c..f4af130a284a3 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl index a6a9d9fe834ff..c4037d16946bd 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl index 91bc4440dc102..5704c6fe5680c 100644 --- a/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar16.cl b/libclc/test/binding/ocl/vloadn_Rchar16.cl index fb5af1fa9591c..cc6ddd06345e5 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar16.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar2.cl b/libclc/test/binding/ocl/vloadn_Rchar2.cl index 2b5a6860a64a1..4ba2b9bd1b38b 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar2.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar3.cl b/libclc/test/binding/ocl/vloadn_Rchar3.cl index 2791ab586c54b..b4019a2820c22 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar3.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar4.cl b/libclc/test/binding/ocl/vloadn_Rchar4.cl index 1af4797e085c3..ef3fa77c56a09 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar4.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rchar8.cl b/libclc/test/binding/ocl/vloadn_Rchar8.cl index e4a69a5e5887d..e03c072e42f4d 100644 --- a/libclc/test/binding/ocl/vloadn_Rchar8.cl +++ b/libclc/test/binding/ocl/vloadn_Rchar8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble16.cl b/libclc/test/binding/ocl/vloadn_Rdouble16.cl index 76a04be4f9800..1baa75932f69f 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble16.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble2.cl b/libclc/test/binding/ocl/vloadn_Rdouble2.cl index 29c92af58c145..a78175c858f5d 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble2.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble3.cl b/libclc/test/binding/ocl/vloadn_Rdouble3.cl index 047d5d23234be..7e6f67cf6aba7 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble3.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble4.cl b/libclc/test/binding/ocl/vloadn_Rdouble4.cl index 0b164112c073f..6c9199efc7501 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble4.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rdouble8.cl b/libclc/test/binding/ocl/vloadn_Rdouble8.cl index 11f6bfbc704f1..fab3d6470e59e 100644 --- a/libclc/test/binding/ocl/vloadn_Rdouble8.cl +++ b/libclc/test/binding/ocl/vloadn_Rdouble8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat16.cl b/libclc/test/binding/ocl/vloadn_Rfloat16.cl index ebf8c4bbd088e..0a9ccbca49ad8 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat16.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat2.cl b/libclc/test/binding/ocl/vloadn_Rfloat2.cl index 64758fb4c28c6..1a2a7fce96ce3 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat2.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat3.cl b/libclc/test/binding/ocl/vloadn_Rfloat3.cl index 8b5546e213702..8d37f39867ed5 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat3.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat4.cl b/libclc/test/binding/ocl/vloadn_Rfloat4.cl index abde3e79bc12c..8ba449cf63d1d 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat4.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rfloat8.cl b/libclc/test/binding/ocl/vloadn_Rfloat8.cl index 15c12d8db5e30..35d19138b7467 100644 --- a/libclc/test/binding/ocl/vloadn_Rfloat8.cl +++ b/libclc/test/binding/ocl/vloadn_Rfloat8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf16.cl b/libclc/test/binding/ocl/vloadn_Rhalf16.cl index 2a0b1f0733d2c..13fbe403451fc 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf16.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf2.cl b/libclc/test/binding/ocl/vloadn_Rhalf2.cl index ef88cea6484f4..38b232c37ae4a 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf2.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf3.cl b/libclc/test/binding/ocl/vloadn_Rhalf3.cl index 98410f7d3717b..de1914637a370 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf3.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf4.cl b/libclc/test/binding/ocl/vloadn_Rhalf4.cl index 01137ec288043..dd67ec602c3a8 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf4.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rhalf8.cl b/libclc/test/binding/ocl/vloadn_Rhalf8.cl index 968245b390a5e..c779ea5e87859 100644 --- a/libclc/test/binding/ocl/vloadn_Rhalf8.cl +++ b/libclc/test/binding/ocl/vloadn_Rhalf8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint16.cl b/libclc/test/binding/ocl/vloadn_Rint16.cl index 4998a0e076f9c..d141ab36f8884 100644 --- a/libclc/test/binding/ocl/vloadn_Rint16.cl +++ b/libclc/test/binding/ocl/vloadn_Rint16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint2.cl b/libclc/test/binding/ocl/vloadn_Rint2.cl index 2bd32a407acd9..e768bc11e7d51 100644 --- a/libclc/test/binding/ocl/vloadn_Rint2.cl +++ b/libclc/test/binding/ocl/vloadn_Rint2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint3.cl b/libclc/test/binding/ocl/vloadn_Rint3.cl index f5c4923df9bd7..2ddab761c9237 100644 --- a/libclc/test/binding/ocl/vloadn_Rint3.cl +++ b/libclc/test/binding/ocl/vloadn_Rint3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint4.cl b/libclc/test/binding/ocl/vloadn_Rint4.cl index b73c72baa235d..f672444b2468e 100644 --- a/libclc/test/binding/ocl/vloadn_Rint4.cl +++ b/libclc/test/binding/ocl/vloadn_Rint4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rint8.cl b/libclc/test/binding/ocl/vloadn_Rint8.cl index 07c69240f82d9..27237ec1bae1a 100644 --- a/libclc/test/binding/ocl/vloadn_Rint8.cl +++ b/libclc/test/binding/ocl/vloadn_Rint8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong16.cl b/libclc/test/binding/ocl/vloadn_Rlong16.cl index 9baf2727c4501..455a4907e0b14 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong16.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong2.cl b/libclc/test/binding/ocl/vloadn_Rlong2.cl index 35a105b86783c..b64065e48804f 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong2.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong3.cl b/libclc/test/binding/ocl/vloadn_Rlong3.cl index 75b53b2afea41..207ee7fe79543 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong3.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong4.cl b/libclc/test/binding/ocl/vloadn_Rlong4.cl index 6594a6ee17382..ca48f124f261e 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong4.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rlong8.cl b/libclc/test/binding/ocl/vloadn_Rlong8.cl index fe45150d1e3db..795bd3d446e3d 100644 --- a/libclc/test/binding/ocl/vloadn_Rlong8.cl +++ b/libclc/test/binding/ocl/vloadn_Rlong8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort16.cl b/libclc/test/binding/ocl/vloadn_Rshort16.cl index 9a45d640ba069..ad74ee6029399 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort16.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort2.cl b/libclc/test/binding/ocl/vloadn_Rshort2.cl index 9ff4871a03040..02e0f086e0ad0 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort2.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort3.cl b/libclc/test/binding/ocl/vloadn_Rshort3.cl index 6a0852126d29c..32b3b8726cf6c 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort3.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort4.cl b/libclc/test/binding/ocl/vloadn_Rshort4.cl index 2c0f6be25256c..5fcffd552dd60 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort4.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rshort8.cl b/libclc/test/binding/ocl/vloadn_Rshort8.cl index 2eeb3d1aee1d3..84d1747965158 100644 --- a/libclc/test/binding/ocl/vloadn_Rshort8.cl +++ b/libclc/test/binding/ocl/vloadn_Rshort8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar16.cl b/libclc/test/binding/ocl/vloadn_Ruchar16.cl index 66342ea644f41..1aebe0191d430 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar16.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar2.cl b/libclc/test/binding/ocl/vloadn_Ruchar2.cl index f4bf238100240..4e0f94da81b42 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar2.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar3.cl b/libclc/test/binding/ocl/vloadn_Ruchar3.cl index b26bdd90be104..8326ada0462ca 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar3.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar4.cl b/libclc/test/binding/ocl/vloadn_Ruchar4.cl index c640093108f41..f2df4aa28abd5 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar4.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruchar8.cl b/libclc/test/binding/ocl/vloadn_Ruchar8.cl index ecef71abba3d4..08c2d2295b4cc 100644 --- a/libclc/test/binding/ocl/vloadn_Ruchar8.cl +++ b/libclc/test/binding/ocl/vloadn_Ruchar8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint16.cl b/libclc/test/binding/ocl/vloadn_Ruint16.cl index d49325ce1bb16..9105f7979bc23 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint16.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint2.cl b/libclc/test/binding/ocl/vloadn_Ruint2.cl index dfc911889818a..bbe03b141059c 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint2.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint3.cl b/libclc/test/binding/ocl/vloadn_Ruint3.cl index 78acd15f09625..bcd6f8b1be7bd 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint3.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint4.cl b/libclc/test/binding/ocl/vloadn_Ruint4.cl index 643ab6253bdba..4870b943d1ee7 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint4.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Ruint8.cl b/libclc/test/binding/ocl/vloadn_Ruint8.cl index 74a01e7b46aa8..147996de2fd77 100644 --- a/libclc/test/binding/ocl/vloadn_Ruint8.cl +++ b/libclc/test/binding/ocl/vloadn_Ruint8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong16.cl b/libclc/test/binding/ocl/vloadn_Rulong16.cl index 145b972f2a548..c590cb1e1f173 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong16.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong2.cl b/libclc/test/binding/ocl/vloadn_Rulong2.cl index e088b8246ca92..ce62abf499fdd 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong2.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong3.cl b/libclc/test/binding/ocl/vloadn_Rulong3.cl index 3f9fa389bfaac..619b38d77649a 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong3.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong4.cl b/libclc/test/binding/ocl/vloadn_Rulong4.cl index b7487e9e49316..cb5adb70a9df6 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong4.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rulong8.cl b/libclc/test/binding/ocl/vloadn_Rulong8.cl index 58a4edcc23c0f..cdccea298787b 100644 --- a/libclc/test/binding/ocl/vloadn_Rulong8.cl +++ b/libclc/test/binding/ocl/vloadn_Rulong8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort16.cl b/libclc/test/binding/ocl/vloadn_Rushort16.cl index c050147b0833f..dd1d7c8214c45 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort16.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort16.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort2.cl b/libclc/test/binding/ocl/vloadn_Rushort2.cl index 6cf667b230739..795b3078cae9b 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort2.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort2.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort3.cl b/libclc/test/binding/ocl/vloadn_Rushort3.cl index 242c407988d35..a0c37eccf4411 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort3.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort3.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort4.cl b/libclc/test/binding/ocl/vloadn_Rushort4.cl index 76825ee509ad1..b69edb7ec1932 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort4.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort4.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vloadn_Rushort8.cl b/libclc/test/binding/ocl/vloadn_Rushort8.cl index a54af575254ba..381199d732a80 100644 --- a/libclc/test/binding/ocl/vloadn_Rushort8.cl +++ b/libclc/test/binding/ocl/vloadn_Rushort8.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_half.cl b/libclc/test/binding/ocl/vstore_half.cl index d47f6950be020..2e601e7f39d14 100644 --- a/libclc/test/binding/ocl/vstore_half.cl +++ b/libclc/test/binding/ocl/vstore_half.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_half_r.cl b/libclc/test/binding/ocl/vstore_half_r.cl index f1d0157984d68..370b470fc4c3b 100644 --- a/libclc/test/binding/ocl/vstore_half_r.cl +++ b/libclc/test/binding/ocl/vstore_half_r.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_halfn.cl b/libclc/test/binding/ocl/vstore_halfn.cl index c87f071383ffa..4285fa20c6428 100644 --- a/libclc/test/binding/ocl/vstore_halfn.cl +++ b/libclc/test/binding/ocl/vstore_halfn.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstore_halfn_r.cl b/libclc/test/binding/ocl/vstore_halfn_r.cl index 7bcdeefae0069..7cf8a23946bdb 100644 --- a/libclc/test/binding/ocl/vstore_halfn_r.cl +++ b/libclc/test/binding/ocl/vstore_halfn_r.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstorea_halfn.cl b/libclc/test/binding/ocl/vstorea_halfn.cl index 9b4d366d661ad..0152b798e9902 100644 --- a/libclc/test/binding/ocl/vstorea_halfn.cl +++ b/libclc/test/binding/ocl/vstorea_halfn.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstorea_halfn_r.cl b/libclc/test/binding/ocl/vstorea_halfn_r.cl index 915c40f532c49..65e2eee261d76 100644 --- a/libclc/test/binding/ocl/vstorea_halfn_r.cl +++ b/libclc/test/binding/ocl/vstorea_halfn_r.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include diff --git a/libclc/test/binding/ocl/vstoren.cl b/libclc/test/binding/ocl/vstoren.cl index 106275b8b64a5..40e43ca01d7be 100644 --- a/libclc/test/binding/ocl/vstoren.cl +++ b/libclc/test/binding/ocl/vstoren.cl @@ -9,12 +9,6 @@ // Autogenerated by gen-libclc-test.py -// INTEL_CUSTOMIZATION -// Mark as unsupported until built-in signature is consistent between libspirv and -// SPV-IR of SPIRV-LLVM-Translator. -// UNSUPPORTED: true -// end INTEL_CUSTOMIZATION - // RUN: %clang -emit-llvm -S -o - %s | FileCheck %s #include From 1f05105b1302f0674d79fa5082a7be31d10710f8 Mon Sep 17 00:00:00 2001 From: Wenju He Date: Mon, 7 Jul 2025 06:15:29 +0200 Subject: [PATCH 3/4] remove unnecessary libclc/test/.clang-format since 48d8f1cdcbd95335c1a4041fa7bcd53bb5ec1a8f --- libclc/test/.clang-format | 1 - 1 file changed, 1 deletion(-) delete mode 100644 libclc/test/.clang-format diff --git a/libclc/test/.clang-format b/libclc/test/.clang-format deleted file mode 100644 index e3845288a2aec..0000000000000 --- a/libclc/test/.clang-format +++ /dev/null @@ -1 +0,0 @@ -DisableFormat: true From 587306abc66cc72508d952f83e9071ce5466ad25 Mon Sep 17 00:00:00 2001 From: Wenju He Date: Tue, 8 Jul 2025 04:30:34 +0200 Subject: [PATCH 4/4] add clang test --- .../spirv-builtin-lookup-convert.cpp | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 clang/test/CodeGenSPIRV/spirv-builtin-lookup-convert.cpp diff --git a/clang/test/CodeGenSPIRV/spirv-builtin-lookup-convert.cpp b/clang/test/CodeGenSPIRV/spirv-builtin-lookup-convert.cpp new file mode 100644 index 0000000000000..48e053318a69f --- /dev/null +++ b/clang/test/CodeGenSPIRV/spirv-builtin-lookup-convert.cpp @@ -0,0 +1,232 @@ +// RUN: %clang_cc1 -triple=spirv64 -fdeclare-spirv-builtins -emit-llvm %s -o - | FileCheck %s + +template struct conditional_t { + using T = If; +}; + +template struct conditional_t { + using T = Else; +}; + +#define DEFINE_TEST_CONVERT_N(Op, N, DstTy, DstTyName, SrcTy, SrcTyName) \ + namespace Op##DstTyName##SrcTyName { \ + using DTy##N = \ + conditional_t::T; \ + using STy##N = \ + conditional_t::T; \ + DTy##N test_##Name##DstTyName(STy##N v) { \ + return __spirv_##Op##Convert_R##DstTyName(v); \ + } \ + STy##N test_##Name##SrcTyName(DTy##N v) { \ + return __spirv_##Op##Convert_R##SrcTyName(v); \ + } \ + } + +#define DEFINE_TEST_CONVERT(Op, DstTy, DstTySpvName, SrcTy, SrcTySpvName) \ + DEFINE_TEST_CONVERT_N(Op, 1, DstTy, DstTySpvName, SrcTy, SrcTySpvName) \ + DEFINE_TEST_CONVERT_N(Op, 2, DstTy, DstTySpvName##2, SrcTy, SrcTySpvName##2) \ + DEFINE_TEST_CONVERT_N(Op, 3, DstTy, DstTySpvName##3, SrcTy, SrcTySpvName##3) \ + DEFINE_TEST_CONVERT_N(Op, 4, DstTy, DstTySpvName##4, SrcTy, SrcTySpvName##4) \ + DEFINE_TEST_CONVERT_N(Op, 8, DstTy, DstTySpvName##8, SrcTy, SrcTySpvName##8) \ + DEFINE_TEST_CONVERT_N(Op, 16, DstTy, DstTySpvName##16, SrcTy, \ + SrcTySpvName##16) + +DEFINE_TEST_CONVERT(S, char, char, short, short) +DEFINE_TEST_CONVERT(S, char, char, int, int) +DEFINE_TEST_CONVERT(S, char, char, long, long) +DEFINE_TEST_CONVERT(S, signed char, schar, int, int) +DEFINE_TEST_CONVERT(S, signed char, schar, short, short) +DEFINE_TEST_CONVERT(S, signed char, schar, long, long) +DEFINE_TEST_CONVERT(S, short, short, int, int) +DEFINE_TEST_CONVERT(S, short, short, long, long) +DEFINE_TEST_CONVERT(S, int, int, long, long) + +DEFINE_TEST_CONVERT(U, unsigned char, uchar, unsigned short, ushort) +DEFINE_TEST_CONVERT(U, unsigned char, uchar, unsigned int, uint) +DEFINE_TEST_CONVERT(U, unsigned char, uchar, unsigned long, ulong) +DEFINE_TEST_CONVERT(U, unsigned short, ushort, unsigned int, uint) +DEFINE_TEST_CONVERT(U, unsigned short, ushort, unsigned long, ulong) +DEFINE_TEST_CONVERT(U, unsigned int, uint, unsigned long, ulong) + +// CHECK: call {{.*}} signext i8 @_Z22__spirv_SConvert_Rchars +// CHECK: call {{.*}} signext i16 @_Z23__spirv_SConvert_Rshortc +// CHECK: call {{.*}} <2 x i8> @_Z23__spirv_SConvert_Rchar2Dv2_s +// CHECK: call {{.*}} <2 x i16> @_Z24__spirv_SConvert_Rshort2Dv2_c +// CHECK: call {{.*}} <3 x i8> @_Z23__spirv_SConvert_Rchar3Dv3_s +// CHECK: call {{.*}} <3 x i16> @_Z24__spirv_SConvert_Rshort3Dv3_c +// CHECK: call {{.*}} <4 x i8> @_Z23__spirv_SConvert_Rchar4Dv4_s +// CHECK: call {{.*}} <4 x i16> @_Z24__spirv_SConvert_Rshort4Dv4_c +// CHECK: call {{.*}} <8 x i8> @_Z23__spirv_SConvert_Rchar8Dv8_s +// CHECK: call {{.*}} <8 x i16> @_Z24__spirv_SConvert_Rshort8Dv8_c +// CHECK: call {{.*}} <16 x i8> @_Z24__spirv_SConvert_Rchar16Dv16_s +// CHECK: call {{.*}} <16 x i16> @_Z25__spirv_SConvert_Rshort16Dv16_c +// CHECK: call {{.*}} signext i8 @_Z22__spirv_SConvert_Rchari +// CHECK: call {{.*}} i32 @_Z21__spirv_SConvert_Rintc +// CHECK: call {{.*}} <2 x i8> @_Z23__spirv_SConvert_Rchar2Dv2_i +// CHECK: call {{.*}} <2 x i32> @_Z22__spirv_SConvert_Rint2Dv2_c +// CHECK: call {{.*}} <3 x i8> @_Z23__spirv_SConvert_Rchar3Dv3_i +// CHECK: call {{.*}} <3 x i32> @_Z22__spirv_SConvert_Rint3Dv3_c +// CHECK: call {{.*}} <4 x i8> @_Z23__spirv_SConvert_Rchar4Dv4_i +// CHECK: call {{.*}} <4 x i32> @_Z22__spirv_SConvert_Rint4Dv4_c +// CHECK: call {{.*}} <8 x i8> @_Z23__spirv_SConvert_Rchar8Dv8_i +// CHECK: call {{.*}} <8 x i32> @_Z22__spirv_SConvert_Rint8Dv8_c +// CHECK: call {{.*}} <16 x i8> @_Z24__spirv_SConvert_Rchar16Dv16_i +// CHECK: call {{.*}} <16 x i32> @_Z23__spirv_SConvert_Rint16Dv16_c +// CHECK: call {{.*}} signext i8 @_Z22__spirv_SConvert_Rcharl +// CHECK: call {{.*}} i64 @_Z22__spirv_SConvert_Rlongc +// CHECK: call {{.*}} <2 x i8> @_Z23__spirv_SConvert_Rchar2Dv2_l +// CHECK: call {{.*}} <2 x i64> @_Z23__spirv_SConvert_Rlong2Dv2_c +// CHECK: call {{.*}} <3 x i8> @_Z23__spirv_SConvert_Rchar3Dv3_l +// CHECK: call {{.*}} <3 x i64> @_Z23__spirv_SConvert_Rlong3Dv3_c +// CHECK: call {{.*}} <4 x i8> @_Z23__spirv_SConvert_Rchar4Dv4_l +// CHECK: call {{.*}} <4 x i64> @_Z23__spirv_SConvert_Rlong4Dv4_c +// CHECK: call {{.*}} <8 x i8> @_Z23__spirv_SConvert_Rchar8Dv8_l +// CHECK: call {{.*}} <8 x i64> @_Z23__spirv_SConvert_Rlong8Dv8_c +// CHECK: call {{.*}} <16 x i8> @_Z24__spirv_SConvert_Rchar16Dv16_l +// CHECK: call {{.*}} <16 x i64> @_Z24__spirv_SConvert_Rlong16Dv16_c +// CHECK: call {{.*}} signext i8 @_Z23__spirv_SConvert_Rschari +// CHECK: call {{.*}} i32 @_Z21__spirv_SConvert_Rinta +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_SConvert_Rschar2Dv2_i +// CHECK: call {{.*}} <2 x i32> @_Z22__spirv_SConvert_Rint2Dv2_a +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_SConvert_Rschar3Dv3_i +// CHECK: call {{.*}} <3 x i32> @_Z22__spirv_SConvert_Rint3Dv3_a +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_SConvert_Rschar4Dv4_i +// CHECK: call {{.*}} <4 x i32> @_Z22__spirv_SConvert_Rint4Dv4_a +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_SConvert_Rschar8Dv8_i +// CHECK: call {{.*}} <8 x i32> @_Z22__spirv_SConvert_Rint8Dv8_a +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_SConvert_Rschar16Dv16_i +// CHECK: call {{.*}} <16 x i32> @_Z23__spirv_SConvert_Rint16Dv16_a +// CHECK: call {{.*}} signext i8 @_Z23__spirv_SConvert_Rschars +// CHECK: call {{.*}} signext i16 @_Z23__spirv_SConvert_Rshorta +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_SConvert_Rschar2Dv2_s +// CHECK: call {{.*}} <2 x i16> @_Z24__spirv_SConvert_Rshort2Dv2_a +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_SConvert_Rschar3Dv3_s +// CHECK: call {{.*}} <3 x i16> @_Z24__spirv_SConvert_Rshort3Dv3_a +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_SConvert_Rschar4Dv4_s +// CHECK: call {{.*}} <4 x i16> @_Z24__spirv_SConvert_Rshort4Dv4_a +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_SConvert_Rschar8Dv8_s +// CHECK: call {{.*}} <8 x i16> @_Z24__spirv_SConvert_Rshort8Dv8_a +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_SConvert_Rschar16Dv16_s +// CHECK: call {{.*}} <16 x i16> @_Z25__spirv_SConvert_Rshort16Dv16_a +// CHECK: call {{.*}} signext i8 @_Z23__spirv_SConvert_Rscharl +// CHECK: call {{.*}} i64 @_Z22__spirv_SConvert_Rlonga +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_SConvert_Rschar2Dv2_l +// CHECK: call {{.*}} <2 x i64> @_Z23__spirv_SConvert_Rlong2Dv2_a +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_SConvert_Rschar3Dv3_l +// CHECK: call {{.*}} <3 x i64> @_Z23__spirv_SConvert_Rlong3Dv3_a +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_SConvert_Rschar4Dv4_l +// CHECK: call {{.*}} <4 x i64> @_Z23__spirv_SConvert_Rlong4Dv4_a +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_SConvert_Rschar8Dv8_l +// CHECK: call {{.*}} <8 x i64> @_Z23__spirv_SConvert_Rlong8Dv8_a +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_SConvert_Rschar16Dv16_l +// CHECK: call {{.*}} <16 x i64> @_Z24__spirv_SConvert_Rlong16Dv16_a +// CHECK: call {{.*}} signext i16 @_Z23__spirv_SConvert_Rshorti +// CHECK: call {{.*}} i32 @_Z21__spirv_SConvert_Rints +// CHECK: call {{.*}} <2 x i16> @_Z24__spirv_SConvert_Rshort2Dv2_i +// CHECK: call {{.*}} <2 x i32> @_Z22__spirv_SConvert_Rint2Dv2_s +// CHECK: call {{.*}} <3 x i16> @_Z24__spirv_SConvert_Rshort3Dv3_i +// CHECK: call {{.*}} <3 x i32> @_Z22__spirv_SConvert_Rint3Dv3_s +// CHECK: call {{.*}} <4 x i16> @_Z24__spirv_SConvert_Rshort4Dv4_i +// CHECK: call {{.*}} <4 x i32> @_Z22__spirv_SConvert_Rint4Dv4_s +// CHECK: call {{.*}} <8 x i16> @_Z24__spirv_SConvert_Rshort8Dv8_i +// CHECK: call {{.*}} <8 x i32> @_Z22__spirv_SConvert_Rint8Dv8_s +// CHECK: call {{.*}} <16 x i16> @_Z25__spirv_SConvert_Rshort16Dv16_i +// CHECK: call {{.*}} <16 x i32> @_Z23__spirv_SConvert_Rint16Dv16_s +// CHECK: call {{.*}} signext i16 @_Z23__spirv_SConvert_Rshortl +// CHECK: call {{.*}} i64 @_Z22__spirv_SConvert_Rlongs +// CHECK: call {{.*}} <2 x i16> @_Z24__spirv_SConvert_Rshort2Dv2_l +// CHECK: call {{.*}} <2 x i64> @_Z23__spirv_SConvert_Rlong2Dv2_s +// CHECK: call {{.*}} <3 x i16> @_Z24__spirv_SConvert_Rshort3Dv3_l +// CHECK: call {{.*}} <3 x i64> @_Z23__spirv_SConvert_Rlong3Dv3_s +// CHECK: call {{.*}} <4 x i16> @_Z24__spirv_SConvert_Rshort4Dv4_l +// CHECK: call {{.*}} <4 x i64> @_Z23__spirv_SConvert_Rlong4Dv4_s +// CHECK: call {{.*}} <8 x i16> @_Z24__spirv_SConvert_Rshort8Dv8_l +// CHECK: call {{.*}} <8 x i64> @_Z23__spirv_SConvert_Rlong8Dv8_s +// CHECK: call {{.*}} <16 x i16> @_Z25__spirv_SConvert_Rshort16Dv16_l +// CHECK: call {{.*}} <16 x i64> @_Z24__spirv_SConvert_Rlong16Dv16_s +// CHECK: call {{.*}} i32 @_Z21__spirv_SConvert_Rintl +// CHECK: call {{.*}} i64 @_Z22__spirv_SConvert_Rlongi +// CHECK: call {{.*}} <2 x i32> @_Z22__spirv_SConvert_Rint2Dv2_l +// CHECK: call {{.*}} <2 x i64> @_Z23__spirv_SConvert_Rlong2Dv2_i +// CHECK: call {{.*}} <3 x i32> @_Z22__spirv_SConvert_Rint3Dv3_l +// CHECK: call {{.*}} <3 x i64> @_Z23__spirv_SConvert_Rlong3Dv3_i +// CHECK: call {{.*}} <4 x i32> @_Z22__spirv_SConvert_Rint4Dv4_l +// CHECK: call {{.*}} <4 x i64> @_Z23__spirv_SConvert_Rlong4Dv4_i +// CHECK: call {{.*}} <8 x i32> @_Z22__spirv_SConvert_Rint8Dv8_l +// CHECK: call {{.*}} <8 x i64> @_Z23__spirv_SConvert_Rlong8Dv8_i +// CHECK: call {{.*}} <16 x i32> @_Z23__spirv_SConvert_Rint16Dv16_l +// CHECK: call {{.*}} <16 x i64> @_Z24__spirv_SConvert_Rlong16Dv16_i +// CHECK: call {{.*}} zeroext i8 @_Z23__spirv_UConvert_Ruchart +// CHECK: call {{.*}} zeroext i16 @_Z24__spirv_UConvert_Rushorth +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_UConvert_Ruchar2Dv2_t +// CHECK: call {{.*}} <2 x i16> @_Z25__spirv_UConvert_Rushort2Dv2_h +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_UConvert_Ruchar3Dv3_t +// CHECK: call {{.*}} <3 x i16> @_Z25__spirv_UConvert_Rushort3Dv3_h +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_UConvert_Ruchar4Dv4_t +// CHECK: call {{.*}} <4 x i16> @_Z25__spirv_UConvert_Rushort4Dv4_h +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_UConvert_Ruchar8Dv8_t +// CHECK: call {{.*}} <8 x i16> @_Z25__spirv_UConvert_Rushort8Dv8_h +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_UConvert_Ruchar16Dv16_t +// CHECK: call {{.*}} <16 x i16> @_Z26__spirv_UConvert_Rushort16Dv16_h +// CHECK: call {{.*}} zeroext i8 @_Z23__spirv_UConvert_Rucharj +// CHECK: call {{.*}} i32 @_Z22__spirv_UConvert_Ruinth +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_UConvert_Ruchar2Dv2_j +// CHECK: call {{.*}} <2 x i32> @_Z23__spirv_UConvert_Ruint2Dv2_h +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_UConvert_Ruchar3Dv3_j +// CHECK: call {{.*}} <3 x i32> @_Z23__spirv_UConvert_Ruint3Dv3_h +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_UConvert_Ruchar4Dv4_j +// CHECK: call {{.*}} <4 x i32> @_Z23__spirv_UConvert_Ruint4Dv4_h +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_UConvert_Ruchar8Dv8_j +// CHECK: call {{.*}} <8 x i32> @_Z23__spirv_UConvert_Ruint8Dv8_h +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_UConvert_Ruchar16Dv16_j +// CHECK: call {{.*}} <16 x i32> @_Z24__spirv_UConvert_Ruint16Dv16_h +// CHECK: call {{.*}} zeroext i8 @_Z23__spirv_UConvert_Rucharm +// CHECK: call {{.*}} i64 @_Z23__spirv_UConvert_Rulongh +// CHECK: call {{.*}} <2 x i8> @_Z24__spirv_UConvert_Ruchar2Dv2_m +// CHECK: call {{.*}} <2 x i64> @_Z24__spirv_UConvert_Rulong2Dv2_h +// CHECK: call {{.*}} <3 x i8> @_Z24__spirv_UConvert_Ruchar3Dv3_m +// CHECK: call {{.*}} <3 x i64> @_Z24__spirv_UConvert_Rulong3Dv3_h +// CHECK: call {{.*}} <4 x i8> @_Z24__spirv_UConvert_Ruchar4Dv4_m +// CHECK: call {{.*}} <4 x i64> @_Z24__spirv_UConvert_Rulong4Dv4_h +// CHECK: call {{.*}} <8 x i8> @_Z24__spirv_UConvert_Ruchar8Dv8_m +// CHECK: call {{.*}} <8 x i64> @_Z24__spirv_UConvert_Rulong8Dv8_h +// CHECK: call {{.*}} <16 x i8> @_Z25__spirv_UConvert_Ruchar16Dv16_m +// CHECK: call {{.*}} <16 x i64> @_Z25__spirv_UConvert_Rulong16Dv16_h +// CHECK: call {{.*}} zeroext i16 @_Z24__spirv_UConvert_Rushortj +// CHECK: call {{.*}} i32 @_Z22__spirv_UConvert_Ruintt +// CHECK: call {{.*}} <2 x i16> @_Z25__spirv_UConvert_Rushort2Dv2_j +// CHECK: call {{.*}} <2 x i32> @_Z23__spirv_UConvert_Ruint2Dv2_t +// CHECK: call {{.*}} <3 x i16> @_Z25__spirv_UConvert_Rushort3Dv3_j +// CHECK: call {{.*}} <3 x i32> @_Z23__spirv_UConvert_Ruint3Dv3_t +// CHECK: call {{.*}} <4 x i16> @_Z25__spirv_UConvert_Rushort4Dv4_j +// CHECK: call {{.*}} <4 x i32> @_Z23__spirv_UConvert_Ruint4Dv4_t +// CHECK: call {{.*}} <8 x i16> @_Z25__spirv_UConvert_Rushort8Dv8_j +// CHECK: call {{.*}} <8 x i32> @_Z23__spirv_UConvert_Ruint8Dv8_t +// CHECK: call {{.*}} <16 x i16> @_Z26__spirv_UConvert_Rushort16Dv16_j +// CHECK: call {{.*}} <16 x i32> @_Z24__spirv_UConvert_Ruint16Dv16_t +// CHECK: call {{.*}} zeroext i16 @_Z24__spirv_UConvert_Rushortm +// CHECK: call {{.*}} i64 @_Z23__spirv_UConvert_Rulongt +// CHECK: call {{.*}} <2 x i16> @_Z25__spirv_UConvert_Rushort2Dv2_m +// CHECK: call {{.*}} <2 x i64> @_Z24__spirv_UConvert_Rulong2Dv2_t +// CHECK: call {{.*}} <3 x i16> @_Z25__spirv_UConvert_Rushort3Dv3_m +// CHECK: call {{.*}} <3 x i64> @_Z24__spirv_UConvert_Rulong3Dv3_t +// CHECK: call {{.*}} <4 x i16> @_Z25__spirv_UConvert_Rushort4Dv4_m +// CHECK: call {{.*}} <4 x i64> @_Z24__spirv_UConvert_Rulong4Dv4_t +// CHECK: call {{.*}} <8 x i16> @_Z25__spirv_UConvert_Rushort8Dv8_m +// CHECK: call {{.*}} <8 x i64> @_Z24__spirv_UConvert_Rulong8Dv8_t +// CHECK: call {{.*}} <16 x i16> @_Z26__spirv_UConvert_Rushort16Dv16_m +// CHECK: call {{.*}} <16 x i64> @_Z25__spirv_UConvert_Rulong16Dv16_t +// CHECK: call {{.*}} i32 @_Z22__spirv_UConvert_Ruintm +// CHECK: call {{.*}} i64 @_Z23__spirv_UConvert_Rulongj +// CHECK: call {{.*}} <2 x i32> @_Z23__spirv_UConvert_Ruint2Dv2_m +// CHECK: call {{.*}} <2 x i64> @_Z24__spirv_UConvert_Rulong2Dv2_j +// CHECK: call {{.*}} <3 x i32> @_Z23__spirv_UConvert_Ruint3Dv3_m +// CHECK: call {{.*}} <3 x i64> @_Z24__spirv_UConvert_Rulong3Dv3_j +// CHECK: call {{.*}} <4 x i32> @_Z23__spirv_UConvert_Ruint4Dv4_m +// CHECK: call {{.*}} <4 x i64> @_Z24__spirv_UConvert_Rulong4Dv4_j +// CHECK: call {{.*}} <8 x i32> @_Z23__spirv_UConvert_Ruint8Dv8_m +// CHECK: call {{.*}} <8 x i64> @_Z24__spirv_UConvert_Rulong8Dv8_j +// CHECK: call {{.*}} <16 x i32> @_Z24__spirv_UConvert_Ruint16Dv16_m +// CHECK: call {{.*}} <16 x i64> @_Z25__spirv_UConvert_Rulong16Dv16_j