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[NFC][AArch64][CodeGen] Add fixed-width vector tests for get.active.lane.mask
In practice we don't expect to see the get.active.lane.mask intrinsic being used for fixed-width vectors, but we should at least be able to generate code for it. This patch simply adds some fixed-width tests to an existing file: CodeGen/AArch64/active_lane_mask.ll Differential Revision: https://reviews.llvm.org/D116644
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‎llvm/test/CodeGen/AArch64/active_lane_mask.ll

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Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; == Scalable ==
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define <vscale x 16 x i1> @lane_mask_nxv16i1_i32(i32 %index, i32 %TC) {
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; CHECK-LABEL: lane_mask_nxv16i1_i32:
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; CHECK: // %bb.0:
@@ -317,6 +319,265 @@ define <vscale x 32 x i1> @lane_mask_nxv32i1_i8(i8 %index, i8 %TC) {
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}
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; == Fixed width ==
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define <16 x i1> @lane_mask_v16i1_i32(i32 %index, i32 %TC) {
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; CHECK-LABEL: lane_mask_v16i1_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI15_0
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; CHECK-NEXT: adrp x9, .LCPI15_3
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; CHECK-NEXT: adrp x10, .LCPI15_2
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; CHECK-NEXT: dup v2.4s, w0
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; CHECK-NEXT: dup v5.4s, w1
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI15_0]
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; CHECK-NEXT: adrp x8, .LCPI15_1
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI15_3]
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; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI15_2]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI15_1]
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; CHECK-NEXT: uqadd v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: uqadd v3.4s, v2.4s, v3.4s
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; CHECK-NEXT: uqadd v4.4s, v2.4s, v4.4s
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; CHECK-NEXT: uqadd v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: cmhi v1.4s, v5.4s, v1.4s
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; CHECK-NEXT: cmhi v2.4s, v5.4s, v3.4s
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; CHECK-NEXT: cmhi v3.4s, v5.4s, v4.4s
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; CHECK-NEXT: cmhi v0.4s, v5.4s, v0.4s
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; CHECK-NEXT: uzp1 v1.8h, v2.8h, v1.8h
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v3.8h
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; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
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ret <16 x i1> %active.lane.mask
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}
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define <8 x i1> @lane_mask_v8i1_i32(i32 %index, i32 %TC) {
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; CHECK-LABEL: lane_mask_v8i1_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI16_1
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; CHECK-NEXT: adrp x9, .LCPI16_0
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; CHECK-NEXT: dup v2.4s, w0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI16_1]
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI16_0]
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; CHECK-NEXT: uqadd v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: uqadd v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: dup v2.4s, w1
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; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: cmhi v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
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ret <8 x i1> %active.lane.mask
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}
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define <4 x i1> @lane_mask_v4i1_i32(i32 %index, i32 %TC) {
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; CHECK-LABEL: lane_mask_v4i1_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI17_0
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI17_0]
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; CHECK-NEXT: uqadd v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: dup v1.4s, w1
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; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
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ret <4 x i1> %active.lane.mask
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}
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define <2 x i1> @lane_mask_v2i1_i32(i32 %index, i32 %TC) {
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; CHECK-LABEL: lane_mask_v2i1_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI18_0
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; CHECK-NEXT: dup v0.2s, w0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI18_0]
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; CHECK-NEXT: uqadd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: dup v1.2s, w1
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; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
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ret <2 x i1> %active.lane.mask
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}
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define <16 x i1> @lane_mask_v16i1_i64(i64 %index, i64 %TC) {
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; CHECK-LABEL: lane_mask_v16i1_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI19_0
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; CHECK-NEXT: adrp x9, .LCPI19_1
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; CHECK-NEXT: adrp x10, .LCPI19_2
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; CHECK-NEXT: dup v1.2d, x0
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; CHECK-NEXT: dup v17.2d, x1
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]
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; CHECK-NEXT: adrp x8, .LCPI19_3
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI19_1]
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; CHECK-NEXT: adrp x9, .LCPI19_4
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; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI19_2]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI19_3]
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; CHECK-NEXT: adrp x8, .LCPI19_5
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI19_4]
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; CHECK-NEXT: adrp x9, .LCPI19_7
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; CHECK-NEXT: uqadd v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: ldr q6, [x8, :lo12:.LCPI19_5]
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; CHECK-NEXT: adrp x8, .LCPI19_6
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; CHECK-NEXT: ldr q7, [x9, :lo12:.LCPI19_7]
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; CHECK-NEXT: uqadd v2.2d, v1.2d, v2.2d
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; CHECK-NEXT: ldr q16, [x8, :lo12:.LCPI19_6]
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; CHECK-NEXT: uqadd v3.2d, v1.2d, v3.2d
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; CHECK-NEXT: uqadd v4.2d, v1.2d, v4.2d
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; CHECK-NEXT: uqadd v6.2d, v1.2d, v6.2d
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; CHECK-NEXT: uqadd v7.2d, v1.2d, v7.2d
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; CHECK-NEXT: uqadd v16.2d, v1.2d, v16.2d
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; CHECK-NEXT: uqadd v1.2d, v1.2d, v5.2d
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; CHECK-NEXT: cmhi v6.2d, v17.2d, v6.2d
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; CHECK-NEXT: cmhi v5.2d, v17.2d, v7.2d
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; CHECK-NEXT: cmhi v7.2d, v17.2d, v16.2d
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; CHECK-NEXT: cmhi v1.2d, v17.2d, v1.2d
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; CHECK-NEXT: cmhi v4.2d, v17.2d, v4.2d
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; CHECK-NEXT: cmhi v3.2d, v17.2d, v3.2d
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; CHECK-NEXT: cmhi v2.2d, v17.2d, v2.2d
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; CHECK-NEXT: cmhi v0.2d, v17.2d, v0.2d
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; CHECK-NEXT: uzp1 v5.4s, v7.4s, v5.4s
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; CHECK-NEXT: uzp1 v1.4s, v1.4s, v6.4s
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; CHECK-NEXT: uzp1 v3.4s, v3.4s, v4.4s
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v5.8h
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v3.8h
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; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 %index, i64 %TC)
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ret <16 x i1> %active.lane.mask
449+
}
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define <8 x i1> @lane_mask_v8i1_i64(i64 %index, i64 %TC) {
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; CHECK-LABEL: lane_mask_v8i1_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI20_0
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; CHECK-NEXT: adrp x9, .LCPI20_3
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; CHECK-NEXT: adrp x10, .LCPI20_2
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; CHECK-NEXT: dup v2.2d, x0
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; CHECK-NEXT: dup v5.2d, x1
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI20_0]
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; CHECK-NEXT: adrp x8, .LCPI20_1
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI20_3]
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; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI20_2]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI20_1]
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; CHECK-NEXT: uqadd v1.2d, v2.2d, v1.2d
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; CHECK-NEXT: uqadd v3.2d, v2.2d, v3.2d
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; CHECK-NEXT: uqadd v4.2d, v2.2d, v4.2d
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; CHECK-NEXT: uqadd v0.2d, v2.2d, v0.2d
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; CHECK-NEXT: cmhi v1.2d, v5.2d, v1.2d
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; CHECK-NEXT: cmhi v2.2d, v5.2d, v3.2d
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; CHECK-NEXT: cmhi v3.2d, v5.2d, v4.2d
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; CHECK-NEXT: cmhi v0.2d, v5.2d, v0.2d
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; CHECK-NEXT: uzp1 v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v3.4s
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %TC)
478+
ret <8 x i1> %active.lane.mask
479+
}
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define <4 x i1> @lane_mask_v4i1_i64(i64 %index, i64 %TC) {
482+
; CHECK-LABEL: lane_mask_v4i1_i64:
483+
; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI21_1
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; CHECK-NEXT: adrp x9, .LCPI21_0
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; CHECK-NEXT: dup v2.2d, x0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI21_1]
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI21_0]
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; CHECK-NEXT: uqadd v0.2d, v2.2d, v0.2d
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; CHECK-NEXT: uqadd v1.2d, v2.2d, v1.2d
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; CHECK-NEXT: dup v2.2d, x1
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; CHECK-NEXT: cmhi v0.2d, v2.2d, v0.2d
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; CHECK-NEXT: cmhi v1.2d, v2.2d, v1.2d
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; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %index, i64 %TC)
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ret <4 x i1> %active.lane.mask
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}
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define <2 x i1> @lane_mask_v2i1_i64(i64 %index, i64 %TC) {
502+
; CHECK-LABEL: lane_mask_v2i1_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI22_0
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; CHECK-NEXT: dup v1.2d, x0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI22_0]
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; CHECK-NEXT: uqadd v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: dup v1.2d, x1
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; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %TC)
513+
ret <2 x i1> %active.lane.mask
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}
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define <16 x i1> @lane_mask_v16i1_i8(i8 %index, i8 %TC) {
517+
; CHECK-LABEL: lane_mask_v16i1_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI23_0
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; CHECK-NEXT: dup v1.16b, w0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_0]
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; CHECK-NEXT: uqadd v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: dup v1.16b, w1
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; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8 %index, i8 %TC)
527+
ret <16 x i1> %active.lane.mask
528+
}
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define <8 x i1> @lane_mask_v8i1_i8(i8 %index, i8 %TC) {
531+
; CHECK-LABEL: lane_mask_v8i1_i8:
532+
; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI24_0
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; CHECK-NEXT: dup v0.8b, w0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI24_0]
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; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: dup v1.8b, w1
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; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: ret
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%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8 %index, i8 %TC)
541+
ret <8 x i1> %active.lane.mask
542+
}
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define <4 x i1> @lane_mask_v4i1_i8(i8 %index, i8 %TC) {
545+
; CHECK-LABEL: lane_mask_v4i1_i8:
546+
; CHECK: // %bb.0:
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; CHECK-NEXT: dup v0.4h, w0
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; CHECK-NEXT: adrp x8, .LCPI25_0
549+
; CHECK-NEXT: dup v2.4h, w1
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI25_0]
551+
; CHECK-NEXT: bic v0.4h, #255, lsl #8
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; CHECK-NEXT: bic v2.4h, #255, lsl #8
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; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
554+
; CHECK-NEXT: movi d1, #0xff00ff00ff00ff
555+
; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: cmhi v0.4h, v2.4h, v0.4h
557+
; CHECK-NEXT: ret
558+
%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC)
559+
ret <4 x i1> %active.lane.mask
560+
}
561+
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define <2 x i1> @lane_mask_v2i1_i8(i8 %index, i8 %TC) {
563+
; CHECK-LABEL: lane_mask_v2i1_i8:
564+
; CHECK: // %bb.0:
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; CHECK-NEXT: movi d0, #0x0000ff000000ff
566+
; CHECK-NEXT: dup v1.2s, w0
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; CHECK-NEXT: adrp x8, .LCPI26_0
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; CHECK-NEXT: dup v3.2s, w1
569+
; CHECK-NEXT: and v1.8b, v1.8b, v0.8b
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; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI26_0]
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; CHECK-NEXT: add v1.2s, v1.2s, v2.2s
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; CHECK-NEXT: and v2.8b, v3.8b, v0.8b
573+
; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: cmhi v0.2s, v2.2s, v0.2s
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; CHECK-NEXT: ret
576+
%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8 %index, i8 %TC)
577+
ret <2 x i1> %active.lane.mask
578+
}
579+
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320581
declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)
321582
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)
322583
declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32, i32)
@@ -334,3 +595,19 @@ declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i8(i8, i8)
334595
declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i8(i8, i8)
335596
declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i8(i8, i8)
336597
declare <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i8(i8, i8)
598+
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
601+
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
603+
declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
606+
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)
607+
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64)
608+
declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8, i8)
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declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8, i8)
612+
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8, i8)
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declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8, i8)

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