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[WebAssembly] Add prototype relaxed laneselect instructions
Add i8x16, i16x8, i32x4, i64x2 laneselect instructions. These are only exposed as builtins, and require user opt-in.
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def

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Original file line numberDiff line numberDiff line change
@@ -167,5 +167,10 @@ TARGET_BUILTIN(__builtin_wasm_fms_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
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TARGET_BUILTIN(__builtin_wasm_fma_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
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TARGET_BUILTIN(__builtin_wasm_fms_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
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170+
TARGET_BUILTIN(__builtin_wasm_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd")
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TARGET_BUILTIN(__builtin_wasm_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
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TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
173+
TARGET_BUILTIN(__builtin_wasm_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd")
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170175
#undef BUILTIN
171176
#undef TARGET_BUILTIN

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18308,6 +18308,17 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1830818308
Function *Callee = CGM.getIntrinsic(IntNo, A->getType());
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return Builder.CreateCall(Callee, {A, B, C});
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}
18311+
case WebAssembly::BI__builtin_wasm_laneselect_i8x16:
18312+
case WebAssembly::BI__builtin_wasm_laneselect_i16x8:
18313+
case WebAssembly::BI__builtin_wasm_laneselect_i32x4:
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case WebAssembly::BI__builtin_wasm_laneselect_i64x2: {
18315+
Value *A = EmitScalarExpr(E->getArg(0));
18316+
Value *B = EmitScalarExpr(E->getArg(1));
18317+
Value *C = EmitScalarExpr(E->getArg(2));
18318+
Function *Callee =
18319+
CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
18320+
return Builder.CreateCall(Callee, {A, B, C});
18321+
}
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default:
1831218323
return nullptr;
1831318324
}

‎clang/test/CodeGen/builtins-wasm.c

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -704,3 +704,31 @@ f64x2 fms_f64x2(f64x2 a, f64x2 b, f64x2 c) {
704704
// WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
705705
// WEBASSEMBLY-NEXT: ret
706706
}
707+
708+
i8x16 laneselect_i8x16(i8x16 a, i8x16 b, i8x16 c) {
709+
return __builtin_wasm_laneselect_i8x16(a, b, c);
710+
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.laneselect.v16i8(
711+
// WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
712+
// WEBASSEMBLY-NEXT: ret
713+
}
714+
715+
i16x8 laneselect_i16x8(i16x8 a, i16x8 b, i16x8 c) {
716+
return __builtin_wasm_laneselect_i16x8(a, b, c);
717+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.laneselect.v8i16(
718+
// WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
719+
// WEBASSEMBLY-NEXT: ret
720+
}
721+
722+
i32x4 laneselect_i32x4(i32x4 a, i32x4 b, i32x4 c) {
723+
return __builtin_wasm_laneselect_i32x4(a, b, c);
724+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.laneselect.v4i32(
725+
// WEBASSEMBLY-SAME: <4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
726+
// WEBASSEMBLY-NEXT: ret
727+
}
728+
729+
i64x2 laneselect_i64x2(i64x2 a, i64x2 b, i64x2 c) {
730+
return __builtin_wasm_laneselect_i64x2(a, b, c);
731+
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.laneselect.v2i64(
732+
// WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
733+
// WEBASSEMBLY-NEXT: ret
734+
}

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,11 @@ def int_wasm_fms :
195195
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
196196
[IntrNoMem, IntrSpeculatable]>;
197197

198+
def int_wasm_laneselect :
199+
Intrinsic<[llvm_anyvector_ty],
200+
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
201+
[IntrNoMem, IntrSpeculatable]>;
202+
198203
//===----------------------------------------------------------------------===//
199204
// Thread-local storage intrinsics
200205
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1344,3 +1344,20 @@ multiclass SIMDFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
13441344

13451345
defm "" : SIMDFM<F32x4, 0xaf, 0xb0>;
13461346
defm "" : SIMDFM<F64x2, 0xcf, 0xd0>;
1347+
1348+
//===----------------------------------------------------------------------===//
1349+
// Laneselect
1350+
//===----------------------------------------------------------------------===//
1351+
1352+
multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
1353+
defm LANESELECT_#vec :
1354+
RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
1355+
[(set (vec.vt V128:$dst), (int_wasm_laneselect
1356+
(vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1357+
vec.prefix#".laneselect\t$dst, $a, $b, $c", vec.prefix#".laneselect", op>;
1358+
}
1359+
1360+
defm "" : SIMDLANESELECT<I8x16, 0xb2>;
1361+
defm "" : SIMDLANESELECT<I16x8, 0xb3>;
1362+
defm "" : SIMDLANESELECT<I32x4, 0xd2>;
1363+
defm "" : SIMDLANESELECT<I64x2, 0xd3>;

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,18 @@ define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
180180
ret <16 x i8> %res
181181
}
182182

183+
; CHECK-LABEL: laneselect_v16i8:
184+
; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
185+
; CHECK-NEXT: i8x16.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
186+
; CHECK-NEXT: return $pop[[R]]{{$}}
187+
declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
188+
define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
189+
%v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
190+
<16 x i8> %a, <16 x i8> %b, <16 x i8> %c
191+
)
192+
ret <16 x i8> %v
193+
}
194+
183195
; ==============================================================================
184196
; 8 x i16
185197
; ==============================================================================
@@ -334,6 +346,18 @@ define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
334346
ret <8 x i16> %a
335347
}
336348

349+
; CHECK-LABEL: laneselect_v8i16:
350+
; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
351+
; CHECK-NEXT: i16x8.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
352+
; CHECK-NEXT: return $pop[[R]]{{$}}
353+
declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
354+
define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
355+
%v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
356+
<8 x i16> %a, <8 x i16> %b, <8 x i16> %c
357+
)
358+
ret <8 x i16> %v
359+
}
360+
337361
; ==============================================================================
338362
; 4 x i32
339363
; ==============================================================================
@@ -480,6 +504,18 @@ define <4 x i32> @trunc_sat_zero_u_v4i32_2(<2 x double> %x) {
480504
ret <4 x i32> %a
481505
}
482506

507+
; CHECK-LABEL: laneselect_v4i32:
508+
; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
509+
; CHECK-NEXT: i32x4.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
510+
; CHECK-NEXT: return $pop[[R]]{{$}}
511+
declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
512+
define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
513+
%v = call <4 x i32> @llvm.wasm.laneselect.v4i32(
514+
<4 x i32> %a, <4 x i32> %b, <4 x i32> %c
515+
)
516+
ret <4 x i32> %v
517+
}
518+
483519
; ==============================================================================
484520
; 2 x i64
485521
; ==============================================================================
@@ -525,6 +561,18 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
525561
ret <2 x i64> %a
526562
}
527563

564+
; CHECK-LABEL: laneselect_v2i64:
565+
; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}}
566+
; CHECK-NEXT: i64x2.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
567+
; CHECK-NEXT: return $pop[[R]]{{$}}
568+
declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
569+
define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
570+
%v = call <2 x i64> @llvm.wasm.laneselect.v2i64(
571+
<2 x i64> %a, <2 x i64> %b, <2 x i64> %c
572+
)
573+
ret <2 x i64> %v
574+
}
575+
528576
; ==============================================================================
529577
; 4 x f32
530578
; ==============================================================================

‎llvm/test/MC/WebAssembly/simd-encodings.s

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -791,4 +791,16 @@ main:
791791
# CHECK: f64x2.fms # encoding: [0xfd,0xd0,0x01]
792792
f64x2.fms
793793

794+
# CHECK: i8x16.laneselect # encoding: [0xfd,0xb2,0x01]
795+
i8x16.laneselect
796+
797+
# CHECK: i16x8.laneselect # encoding: [0xfd,0xb3,0x01]
798+
i16x8.laneselect
799+
800+
# CHECK: i32x4.laneselect # encoding: [0xfd,0xd2,0x01]
801+
i32x4.laneselect
802+
803+
# CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
804+
i64x2.laneselect
805+
794806
end_function

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