[AMDGPU] Set MemoryVT for truncstores in tblgen.

GlobalISelEmitter was skipping these patterns when its predicates were
checked. This patch should allow us to select d16_hi stores in
GlobalISel.

Differential Revision: https://reviews.llvm.org/D117762

Author: Abinav Puthan Purayil

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

@@ -406,9 +406,10 @@ class Aligned<int Bytes> {
   int MinAlignment = Bytes;
 }
 
-class StoreHi16<SDPatternOperator op> : PatFrag <
+class StoreHi16<SDPatternOperator op, ValueType vt> : PatFrag <
   (ops node:$value, node:$ptr), (op (srl node:$value, (i32 16)), node:$ptr)> {
   let IsStore = 1;
+  let MemoryVT = vt;
 }
 
 def LoadAddress_constant : AddressSpaceList<[ AddrSpaces.Constant,
@@ -527,9 +528,9 @@ def truncstorei16_#as : PatFrag<(ops node:$val, node:$ptr),
   let MemoryVT = i16;
 }
 
-def store_hi16_#as : StoreHi16 <truncstorei16>;
-def truncstorei8_hi16_#as : StoreHi16<truncstorei8>;
-def truncstorei16_hi16_#as : StoreHi16<truncstorei16>;
+def store_hi16_#as : StoreHi16 <truncstorei16, i16>;
+def truncstorei8_hi16_#as : StoreHi16<truncstorei8, i8>;
+def truncstorei16_hi16_#as : StoreHi16<truncstorei16, i16>;
 
 defm atomic_store_#as : binary_atomic_op<atomic_store>;
 

llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll

@@ -268,30 +268,30 @@ define void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
 ; GFX10-NEXT:    v_lshrrev_b16 v6, 8, v1
 ; GFX10-NEXT:    ds_write_b8 v0, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX10-NEXT:    v_lshrrev_b16 v8, 8, v2
-; GFX10-NEXT:    v_lshrrev_b16 v7, 8, v5
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v1 offset:2
+; GFX10-NEXT:    v_lshrrev_b16 v7, 8, v2
+; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v5
+; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
 ; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
 ; GFX10-NEXT:    ds_write_b8 v0, v6 offset:1
-; GFX10-NEXT:    ds_write_b8 v0, v5 offset:2
-; GFX10-NEXT:    ds_write_b8 v0, v7 offset:3
-; GFX10-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX10-NEXT:    ds_write_b8 v0, v8 offset:5
-; GFX10-NEXT:    ds_write_b8 v0, v1 offset:6
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX10-NEXT:    ds_write_b8 v0, v1 offset:3
+; GFX10-NEXT:    ds_write_b8 v0, v7 offset:5
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v2 offset:6
+; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v5
 ; GFX10-NEXT:    v_lshrrev_b16 v5, 8, v3
-; GFX10-NEXT:    ds_write_b8 v0, v2 offset:7
+; GFX10-NEXT:    ds_write_b8 v0, v1 offset:7
 ; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX10-NEXT:    v_lshrrev_b16 v3, 8, v1
+; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX10-NEXT:    v_lshrrev_b16 v2, 8, v2
 ; GFX10-NEXT:    ds_write_b8 v0, v5 offset:9
 ; GFX10-NEXT:    v_lshrrev_b16 v5, 8, v4
-; GFX10-NEXT:    ds_write_b8 v0, v1 offset:10
-; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v2
-; GFX10-NEXT:    ds_write_b8 v0, v3 offset:11
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v3 offset:10
+; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v1
+; GFX10-NEXT:    ds_write_b8 v0, v2 offset:11
 ; GFX10-NEXT:    ds_write_b8 v0, v4 offset:12
 ; GFX10-NEXT:    ds_write_b8 v0, v5 offset:13
-; GFX10-NEXT:    ds_write_b8 v0, v2 offset:14
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v4 offset:14
 ; GFX10-NEXT:    ds_write_b8 v0, v1 offset:15
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -342,24 +342,24 @@ define void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
 ; GFX10-NEXT:    v_lshrrev_b16 v5, 8, v1
 ; GFX10-NEXT:    ds_write_b8 v0, v1
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v1 offset:2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX10-NEXT:    v_lshrrev_b16 v4, 8, v4
 ; GFX10-NEXT:    v_lshrrev_b16 v6, 8, v2
-; GFX10-NEXT:    v_lshrrev_b16 v7, 8, v4
 ; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v1
 ; GFX10-NEXT:    ds_write_b8 v0, v5 offset:1
-; GFX10-NEXT:    ds_write_b8 v0, v4 offset:2
-; GFX10-NEXT:    ds_write_b8 v0, v7 offset:3
-; GFX10-NEXT:    v_lshrrev_b16 v4, 8, v1
-; GFX10-NEXT:    v_lshrrev_b16 v5, 8, v3
-; GFX10-NEXT:    ds_write_b8 v0, v1 offset:6
-; GFX10-NEXT:    v_lshrrev_b16 v1, 8, v2
+; GFX10-NEXT:    ds_write_b8 v0, v4 offset:3
+; GFX10-NEXT:    v_lshrrev_b16 v4, 8, v3
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v2 offset:6
+; GFX10-NEXT:    v_lshrrev_b16 v2, 8, v7
 ; GFX10-NEXT:    ds_write_b8 v0, v6 offset:5
-; GFX10-NEXT:    ds_write_b8 v0, v4 offset:7
+; GFX10-NEXT:    ds_write_b8 v0, v1 offset:7
 ; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
-; GFX10-NEXT:    ds_write_b8 v0, v5 offset:9
-; GFX10-NEXT:    ds_write_b8 v0, v2 offset:10
-; GFX10-NEXT:    ds_write_b8 v0, v1 offset:11
+; GFX10-NEXT:    ds_write_b8 v0, v4 offset:9
+; GFX10-NEXT:    ds_write_b8_d16_hi v0, v3 offset:10
+; GFX10-NEXT:    ds_write_b8 v0, v2 offset:11
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1

llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll

@@ -356,9 +356,8 @@ define amdgpu_kernel void @constant_sextload_i8_align2(i32 addrspace(1)* %out, i
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_sbyte v1, v0, s[2:3]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
-; GFX9-NEXT:    global_store_short v0, v2, s[0:1] offset:2
+; GFX9-NEXT:    global_store_short_d16_hi v0, v1, s[0:1] offset:2
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: constant_sextload_i8_align2:
@@ -368,9 +367,8 @@ define amdgpu_kernel void @constant_sextload_i8_align2(i32 addrspace(1)* %out, i
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_sbyte v1, v0, s[2:3]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
-; GFX10-NEXT:    global_store_short v0, v2, s[0:1] offset:2
+; GFX10-NEXT:    global_store_short_d16_hi v0, v1, s[0:1] offset:2
 ; GFX10-NEXT:    s_endpgm
   %load = load i8, i8 addrspace(1)* %in, align 2
   %sextload = sext i8 %load to i32
@@ -405,9 +403,8 @@ define amdgpu_kernel void @constant_zextload_i8_align2(i32 addrspace(1)* %out, i
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ubyte v1, v0, s[2:3]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
-; GFX9-NEXT:    global_store_short v0, v2, s[0:1] offset:2
+; GFX9-NEXT:    global_store_short_d16_hi v0, v1, s[0:1] offset:2
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: constant_zextload_i8_align2:
@@ -417,9 +414,8 @@ define amdgpu_kernel void @constant_zextload_i8_align2(i32 addrspace(1)* %out, i
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_ubyte v1, v0, s[2:3]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
-; GFX10-NEXT:    global_store_short v0, v2, s[0:1] offset:2
+; GFX10-NEXT:    global_store_short_d16_hi v0, v1, s[0:1] offset:2
 ; GFX10-NEXT:    s_endpgm
   %load = load i8, i8 addrspace(1)* %in, align 2
   %zextload = zext i8 %load to i32