Skip to content

Commit d78fe84

Browse files
topperctopperc
authored
[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)
1 parent ae26f50 commit d78fe84

File tree

17 files changed

+246
-283
lines changed

17 files changed

+246
-283
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,8 @@ class RISCVInstructionSelector : public InstructionSelector {
134134

135135
void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
136136
int OpIdx) const;
137+
void renderXLenSubTrailingOnes(MachineInstrBuilder &MIB,
138+
const MachineInstr &MI, int OpIdx) const;
137139

138140
const RISCVSubtarget &STI;
139141
const RISCVInstrInfo &TII;
@@ -861,6 +863,14 @@ void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
861863
MIB.addImm(llvm::countr_zero(C));
862864
}
863865

866+
void RISCVInstructionSelector::renderXLenSubTrailingOnes(
867+
MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
868+
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
869+
"Expected G_CONSTANT");
870+
uint64_t C = MI.getOperand(1).getCImm()->getZExtValue();
871+
MIB.addImm(Subtarget->getXLen() - llvm::countr_one(C));
872+
}
873+
864874
const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
865875
LLT Ty, const RegisterBank &RB) const {
866876
if (RB.getID() == RISCV::GPRBRegBankID) {

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -476,6 +476,8 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
476476
return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
477477
N->getValueType(0));
478478
}]>;
479+
def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
480+
GISDNodeXFormEquiv<XLenSubTrailingOnes>;
479481

480482
// Checks if this mask is a non-empty sequence of ones starting at the
481483
// most/least significant bit with the remainder zero and exceeds simm32/simm12.
@@ -489,7 +491,15 @@ def TrailingOnesMask : PatLeaf<(imm), [{
489491
if (!N->hasOneUse())
490492
return false;
491493
return !isInt<12>(N->getSExtValue()) && isMask_64(N->getZExtValue());
492-
}], XLenSubTrailingOnes>;
494+
}], XLenSubTrailingOnes> {
495+
let GISelPredicateCode = [{
496+
if (!MRI.hasOneNonDBGUse(MI.getOperand(0).getReg()))
497+
return false;
498+
const auto &MO = MI.getOperand(1);
499+
return !isInt<12>(MO.getCImm()->getSExtValue()) &&
500+
isMask_64(MO.getCImm()->getZExtValue());
501+
}];
502+
}
493503

494504
// Similar to LeadingOnesMask, but only consider leading ones in the lower 32
495505
// bits.

‎llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -161,19 +161,19 @@ define double @fsgnj_d(double %a, double %b) nounwind {
161161
; RV32I-LABEL: fsgnj_d:
162162
; RV32I: # %bb.0:
163163
; RV32I-NEXT: lui a2, 524288
164-
; RV32I-NEXT: addi a4, a2, -1
165-
; RV32I-NEXT: and a1, a1, a4
164+
; RV32I-NEXT: slli a1, a1, 1
165+
; RV32I-NEXT: srli a1, a1, 1
166166
; RV32I-NEXT: and a2, a3, a2
167167
; RV32I-NEXT: or a1, a1, a2
168168
; RV32I-NEXT: ret
169169
;
170170
; RV64I-LABEL: fsgnj_d:
171171
; RV64I: # %bb.0:
172172
; RV64I-NEXT: li a2, -1
173-
; RV64I-NEXT: slli a3, a2, 63
174-
; RV64I-NEXT: srli a2, a2, 1
175-
; RV64I-NEXT: and a0, a0, a2
176-
; RV64I-NEXT: and a1, a1, a3
173+
; RV64I-NEXT: slli a0, a0, 1
174+
; RV64I-NEXT: slli a2, a2, 63
175+
; RV64I-NEXT: srli a0, a0, 1
176+
; RV64I-NEXT: and a1, a1, a2
177177
; RV64I-NEXT: or a0, a0, a1
178178
; RV64I-NEXT: ret
179179
%1 = call double @llvm.copysign.f64(double %a, double %b)
@@ -241,21 +241,21 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
241241
; RV32I-LABEL: fsgnjn_d:
242242
; RV32I: # %bb.0:
243243
; RV32I-NEXT: lui a2, 524288
244+
; RV32I-NEXT: slli a1, a1, 1
244245
; RV32I-NEXT: xor a3, a3, a2
245-
; RV32I-NEXT: addi a4, a2, -1
246-
; RV32I-NEXT: and a1, a1, a4
246+
; RV32I-NEXT: srli a1, a1, 1
247247
; RV32I-NEXT: and a2, a3, a2
248248
; RV32I-NEXT: or a1, a1, a2
249249
; RV32I-NEXT: ret
250250
;
251251
; RV64I-LABEL: fsgnjn_d:
252252
; RV64I: # %bb.0:
253253
; RV64I-NEXT: li a2, -1
254-
; RV64I-NEXT: slli a3, a2, 63
255-
; RV64I-NEXT: srli a2, a2, 1
256-
; RV64I-NEXT: xor a1, a1, a3
257-
; RV64I-NEXT: and a0, a0, a2
258-
; RV64I-NEXT: and a1, a1, a3
254+
; RV64I-NEXT: slli a0, a0, 1
255+
; RV64I-NEXT: slli a2, a2, 63
256+
; RV64I-NEXT: xor a1, a1, a2
257+
; RV64I-NEXT: srli a0, a0, 1
258+
; RV64I-NEXT: and a1, a1, a2
259259
; RV64I-NEXT: or a0, a0, a1
260260
; RV64I-NEXT: ret
261261
%1 = fneg double %b
@@ -281,9 +281,8 @@ define double @fabs_d(double %a, double %b) nounwind {
281281
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
282282
; RV32I-NEXT: call __adddf3
283283
; RV32I-NEXT: mv a3, a1
284-
; RV32I-NEXT: lui a1, 524288
285-
; RV32I-NEXT: addi a1, a1, -1
286-
; RV32I-NEXT: and a1, a3, a1
284+
; RV32I-NEXT: slli a1, a1, 1
285+
; RV32I-NEXT: srli a1, a1, 1
287286
; RV32I-NEXT: mv a2, a0
288287
; RV32I-NEXT: call __adddf3
289288
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -296,9 +295,8 @@ define double @fabs_d(double %a, double %b) nounwind {
296295
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
297296
; RV64I-NEXT: call __adddf3
298297
; RV64I-NEXT: mv a1, a0
299-
; RV64I-NEXT: li a0, -1
298+
; RV64I-NEXT: slli a0, a0, 1
300299
; RV64I-NEXT: srli a0, a0, 1
301-
; RV64I-NEXT: and a0, a1, a0
302300
; RV64I-NEXT: call __adddf3
303301
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
304302
; RV64I-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -787,27 +787,24 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
787787
; RV32IFD-LABEL: fcvt_wu_s_i16:
788788
; RV32IFD: # %bb.0:
789789
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
790-
; RV32IFD-NEXT: lui a1, 16
791-
; RV32IFD-NEXT: addi a1, a1, -1
792-
; RV32IFD-NEXT: and a0, a0, a1
790+
; RV32IFD-NEXT: slli a0, a0, 16
791+
; RV32IFD-NEXT: srli a0, a0, 16
793792
; RV32IFD-NEXT: ret
794793
;
795794
; RV64IFD-LABEL: fcvt_wu_s_i16:
796795
; RV64IFD: # %bb.0:
797796
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
798-
; RV64IFD-NEXT: lui a1, 16
799-
; RV64IFD-NEXT: addiw a1, a1, -1
800-
; RV64IFD-NEXT: and a0, a0, a1
797+
; RV64IFD-NEXT: slli a0, a0, 48
798+
; RV64IFD-NEXT: srli a0, a0, 48
801799
; RV64IFD-NEXT: ret
802800
;
803801
; RV32I-LABEL: fcvt_wu_s_i16:
804802
; RV32I: # %bb.0:
805803
; RV32I-NEXT: addi sp, sp, -16
806804
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
807805
; RV32I-NEXT: call __fixunsdfsi
808-
; RV32I-NEXT: lui a1, 16
809-
; RV32I-NEXT: addi a1, a1, -1
810-
; RV32I-NEXT: and a0, a0, a1
806+
; RV32I-NEXT: slli a0, a0, 16
807+
; RV32I-NEXT: srli a0, a0, 16
811808
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
812809
; RV32I-NEXT: addi sp, sp, 16
813810
; RV32I-NEXT: ret
@@ -817,9 +814,8 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
817814
; RV64I-NEXT: addi sp, sp, -16
818815
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
819816
; RV64I-NEXT: call __fixunsdfsi
820-
; RV64I-NEXT: lui a1, 16
821-
; RV64I-NEXT: addiw a1, a1, -1
822-
; RV64I-NEXT: and a0, a0, a1
817+
; RV64I-NEXT: slli a0, a0, 48
818+
; RV64I-NEXT: srli a0, a0, 48
823819
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
824820
; RV64I-NEXT: addi sp, sp, 16
825821
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -631,16 +631,14 @@ define double @fabs_f64(double %a) nounwind {
631631
;
632632
; RV32I-LABEL: fabs_f64:
633633
; RV32I: # %bb.0:
634-
; RV32I-NEXT: lui a2, 524288
635-
; RV32I-NEXT: addi a2, a2, -1
636-
; RV32I-NEXT: and a1, a1, a2
634+
; RV32I-NEXT: slli a1, a1, 1
635+
; RV32I-NEXT: srli a1, a1, 1
637636
; RV32I-NEXT: ret
638637
;
639638
; RV64I-LABEL: fabs_f64:
640639
; RV64I: # %bb.0:
641-
; RV64I-NEXT: li a1, -1
642-
; RV64I-NEXT: srli a1, a1, 1
643-
; RV64I-NEXT: and a0, a0, a1
640+
; RV64I-NEXT: slli a0, a0, 1
641+
; RV64I-NEXT: srli a0, a0, 1
644642
; RV64I-NEXT: ret
645643
%1 = call double @llvm.fabs.f64(double %a)
646644
ret double %1
@@ -715,19 +713,19 @@ define double @copysign_f64(double %a, double %b) nounwind {
715713
; RV32I-LABEL: copysign_f64:
716714
; RV32I: # %bb.0:
717715
; RV32I-NEXT: lui a2, 524288
718-
; RV32I-NEXT: addi a4, a2, -1
719-
; RV32I-NEXT: and a1, a1, a4
716+
; RV32I-NEXT: slli a1, a1, 1
717+
; RV32I-NEXT: srli a1, a1, 1
720718
; RV32I-NEXT: and a2, a3, a2
721719
; RV32I-NEXT: or a1, a1, a2
722720
; RV32I-NEXT: ret
723721
;
724722
; RV64I-LABEL: copysign_f64:
725723
; RV64I: # %bb.0:
726724
; RV64I-NEXT: li a2, -1
727-
; RV64I-NEXT: slli a3, a2, 63
728-
; RV64I-NEXT: srli a2, a2, 1
729-
; RV64I-NEXT: and a0, a0, a2
730-
; RV64I-NEXT: and a1, a1, a3
725+
; RV64I-NEXT: slli a0, a0, 1
726+
; RV64I-NEXT: slli a2, a2, 63
727+
; RV64I-NEXT: srli a0, a0, 1
728+
; RV64I-NEXT: and a1, a1, a2
731729
; RV64I-NEXT: or a0, a0, a1
732730
; RV64I-NEXT: ret
733731
%1 = call double @llvm.copysign.f64(double %a, double %b)
@@ -1039,10 +1037,9 @@ define i1 @isnan_d_fpclass(double %x) {
10391037
;
10401038
; RV32I-LABEL: isnan_d_fpclass:
10411039
; RV32I: # %bb.0:
1042-
; RV32I-NEXT: lui a2, 524288
1043-
; RV32I-NEXT: addi a3, a2, -1
10441040
; RV32I-NEXT: lui a2, 524032
1045-
; RV32I-NEXT: and a1, a1, a3
1041+
; RV32I-NEXT: slli a1, a1, 1
1042+
; RV32I-NEXT: srli a1, a1, 1
10461043
; RV32I-NEXT: beq a1, a2, .LBB25_2
10471044
; RV32I-NEXT: # %bb.1:
10481045
; RV32I-NEXT: sltu a0, a2, a1
@@ -1053,12 +1050,11 @@ define i1 @isnan_d_fpclass(double %x) {
10531050
;
10541051
; RV64I-LABEL: isnan_d_fpclass:
10551052
; RV64I: # %bb.0:
1056-
; RV64I-NEXT: li a1, -1
1057-
; RV64I-NEXT: li a2, 2047
1058-
; RV64I-NEXT: srli a1, a1, 1
1059-
; RV64I-NEXT: slli a2, a2, 52
1060-
; RV64I-NEXT: and a0, a0, a1
1061-
; RV64I-NEXT: sltu a0, a2, a0
1053+
; RV64I-NEXT: li a1, 2047
1054+
; RV64I-NEXT: slli a0, a0, 1
1055+
; RV64I-NEXT: slli a1, a1, 52
1056+
; RV64I-NEXT: srli a0, a0, 1
1057+
; RV64I-NEXT: sltu a0, a1, a0
10621058
; RV64I-NEXT: ret
10631059
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
10641060
ret i1 %1

‎llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -161,17 +161,17 @@ define float @fsgnj_s(float %a, float %b) nounwind {
161161
; RV32I-LABEL: fsgnj_s:
162162
; RV32I: # %bb.0:
163163
; RV32I-NEXT: lui a2, 524288
164-
; RV32I-NEXT: addi a3, a2, -1
165-
; RV32I-NEXT: and a0, a0, a3
164+
; RV32I-NEXT: slli a0, a0, 1
165+
; RV32I-NEXT: srli a0, a0, 1
166166
; RV32I-NEXT: and a1, a1, a2
167167
; RV32I-NEXT: or a0, a0, a1
168168
; RV32I-NEXT: ret
169169
;
170170
; RV64I-LABEL: fsgnj_s:
171171
; RV64I: # %bb.0:
172172
; RV64I-NEXT: lui a2, 524288
173-
; RV64I-NEXT: addiw a3, a2, -1
174-
; RV64I-NEXT: and a0, a0, a3
173+
; RV64I-NEXT: slli a0, a0, 33
174+
; RV64I-NEXT: srli a0, a0, 33
175175
; RV64I-NEXT: and a1, a1, a2
176176
; RV64I-NEXT: or a0, a0, a1
177177
; RV64I-NEXT: ret
@@ -238,11 +238,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
238238
; RV32I-NEXT: mv s0, a0
239239
; RV32I-NEXT: call __addsf3
240240
; RV32I-NEXT: lui a1, 524288
241+
; RV32I-NEXT: slli s0, s0, 1
241242
; RV32I-NEXT: xor a0, a0, a1
242-
; RV32I-NEXT: addi a2, a1, -1
243-
; RV32I-NEXT: and a2, s0, a2
243+
; RV32I-NEXT: srli s0, s0, 1
244244
; RV32I-NEXT: and a0, a0, a1
245-
; RV32I-NEXT: or a0, a2, a0
245+
; RV32I-NEXT: or a0, s0, a0
246246
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
247247
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
248248
; RV32I-NEXT: addi sp, sp, 16
@@ -256,11 +256,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
256256
; RV64I-NEXT: mv s0, a0
257257
; RV64I-NEXT: call __addsf3
258258
; RV64I-NEXT: lui a1, 524288
259+
; RV64I-NEXT: slli s0, s0, 33
259260
; RV64I-NEXT: xor a0, a0, a1
260-
; RV64I-NEXT: addiw a2, a1, -1
261-
; RV64I-NEXT: and a2, s0, a2
261+
; RV64I-NEXT: srli s0, s0, 33
262262
; RV64I-NEXT: and a0, a0, a1
263-
; RV64I-NEXT: or a0, a2, a0
263+
; RV64I-NEXT: or a0, s0, a0
264264
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
265265
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
266266
; RV64I-NEXT: addi sp, sp, 16
@@ -287,9 +287,8 @@ define float @fabs_s(float %a, float %b) nounwind {
287287
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
288288
; RV32I-NEXT: call __addsf3
289289
; RV32I-NEXT: mv a1, a0
290-
; RV32I-NEXT: lui a0, 524288
291-
; RV32I-NEXT: addi a0, a0, -1
292-
; RV32I-NEXT: and a0, a1, a0
290+
; RV32I-NEXT: slli a0, a0, 1
291+
; RV32I-NEXT: srli a0, a0, 1
293292
; RV32I-NEXT: call __addsf3
294293
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
295294
; RV32I-NEXT: addi sp, sp, 16
@@ -301,9 +300,8 @@ define float @fabs_s(float %a, float %b) nounwind {
301300
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
302301
; RV64I-NEXT: call __addsf3
303302
; RV64I-NEXT: mv a1, a0
304-
; RV64I-NEXT: lui a0, 524288
305-
; RV64I-NEXT: addiw a0, a0, -1
306-
; RV64I-NEXT: and a0, a1, a0
303+
; RV64I-NEXT: slli a0, a0, 33
304+
; RV64I-NEXT: srli a0, a0, 33
307305
; RV64I-NEXT: call __addsf3
308306
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
309307
; RV64I-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -722,27 +722,24 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
722722
; RV32IF-LABEL: fcvt_wu_s_i16:
723723
; RV32IF: # %bb.0:
724724
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
725-
; RV32IF-NEXT: lui a1, 16
726-
; RV32IF-NEXT: addi a1, a1, -1
727-
; RV32IF-NEXT: and a0, a0, a1
725+
; RV32IF-NEXT: slli a0, a0, 16
726+
; RV32IF-NEXT: srli a0, a0, 16
728727
; RV32IF-NEXT: ret
729728
;
730729
; RV64IF-LABEL: fcvt_wu_s_i16:
731730
; RV64IF: # %bb.0:
732731
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
733-
; RV64IF-NEXT: lui a1, 16
734-
; RV64IF-NEXT: addiw a1, a1, -1
735-
; RV64IF-NEXT: and a0, a0, a1
732+
; RV64IF-NEXT: slli a0, a0, 48
733+
; RV64IF-NEXT: srli a0, a0, 48
736734
; RV64IF-NEXT: ret
737735
;
738736
; RV32I-LABEL: fcvt_wu_s_i16:
739737
; RV32I: # %bb.0:
740738
; RV32I-NEXT: addi sp, sp, -16
741739
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
742740
; RV32I-NEXT: call __fixunssfsi
743-
; RV32I-NEXT: lui a1, 16
744-
; RV32I-NEXT: addi a1, a1, -1
745-
; RV32I-NEXT: and a0, a0, a1
741+
; RV32I-NEXT: slli a0, a0, 16
742+
; RV32I-NEXT: srli a0, a0, 16
746743
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
747744
; RV32I-NEXT: addi sp, sp, 16
748745
; RV32I-NEXT: ret
@@ -752,9 +749,8 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
752749
; RV64I-NEXT: addi sp, sp, -16
753750
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
754751
; RV64I-NEXT: call __fixunssfsi
755-
; RV64I-NEXT: lui a1, 16
756-
; RV64I-NEXT: addiw a1, a1, -1
757-
; RV64I-NEXT: and a0, a0, a1
752+
; RV64I-NEXT: slli a0, a0, 48
753+
; RV64I-NEXT: srli a0, a0, 48
758754
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
759755
; RV64I-NEXT: addi sp, sp, 16
760756
; RV64I-NEXT: ret

0 commit comments

Comments
 (0)