|
1 |
| -//===----------------------------------------------------------------------===// |
2 |
| -// |
3 |
| -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 |
| -// See https://llvm.org/LICENSE.txt for license information. |
5 |
| -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 |
| -// |
7 |
| -//===----------------------------------------------------------------------===// |
8 |
| - |
9 |
| -#include <atomic_helpers.h> |
10 |
| -#include <libspirv/spirv.h> |
11 |
| -#include <libspirv/spirv_types.h> |
12 |
| - |
13 |
| -extern int __clc_nvvm_reflect_arch(); |
14 |
| -_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int); |
15 |
| - |
16 |
| -#define __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
17 |
| - ADDR_SPACE, ADDR_SPACE_NV, ORDER) \ |
18 |
| - switch (scope) { \ |
19 |
| - case Invocation: \ |
20 |
| - case Subgroup: \ |
21 |
| - case Workgroup: { \ |
22 |
| - TYPE_NV res = __nvvm##ORDER##_cta_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
23 |
| - (ADDR_SPACE TYPE_NV *)pointer); \ |
24 |
| - return *(TYPE *)&res; \ |
25 |
| - } \ |
26 |
| - case Device: { \ |
27 |
| - TYPE_NV res = __nvvm##ORDER##_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
28 |
| - (ADDR_SPACE TYPE_NV *)pointer); \ |
29 |
| - return *(TYPE *)&res; \ |
30 |
| - } \ |
31 |
| - case CrossDevice: \ |
32 |
| - default: { \ |
33 |
| - TYPE_NV res = __nvvm##ORDER##_sys_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
34 |
| - (ADDR_SPACE TYPE_NV *)pointer); \ |
35 |
| - return *(TYPE *)&res; \ |
36 |
| - } \ |
37 |
| - } |
38 |
| - |
39 |
| -#define __CLC_NVVM_ATOMIC_LOAD_IMPL( \ |
40 |
| - TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, ADDR_SPACE, \ |
41 |
| - POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \ |
42 |
| - __attribute__((always_inline)) _CLC_DECL TYPE _Z18__spirv_\ |
43 |
| -AtomicLoad##POINTER_AND_ADDR_SPACE_MANGLED##K##TYPE_MANGLED##N5__spv5\ |
44 |
| -Scope4FlagENS1_19MemorySemanticsMask4FlagE( \ |
45 |
| - const volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \ |
46 |
| - enum MemorySemanticsMask semantics) { \ |
47 |
| - /* Semantics mask may include memory order, storage class and other info \ |
48 |
| -Memory order is stored in the lowest 5 bits */ \ |
49 |
| - unsigned int order = semantics & 0x1F; \ |
50 |
| - if (__clc_nvvm_reflect_arch() >= 700) { \ |
51 |
| - switch (order) { \ |
52 |
| - case None: \ |
53 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
54 |
| - ADDR_SPACE, ADDR_SPACE_NV, ) \ |
55 |
| - case Acquire: \ |
56 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
57 |
| - ADDR_SPACE, ADDR_SPACE_NV, _acquire) \ |
58 |
| - break; \ |
59 |
| - case SequentiallyConsistent: \ |
60 |
| - __CLC_NVVM_FENCE_SC_SM70() \ |
61 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
62 |
| - ADDR_SPACE, ADDR_SPACE_NV, _acquire) \ |
63 |
| - break; \ |
64 |
| - } \ |
65 |
| - } else { \ |
66 |
| - TYPE_NV res = __nvvm_volatile_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
67 |
| - (ADDR_SPACE TYPE_NV *)pointer); \ |
68 |
| - switch (order) { \ |
69 |
| - case None: \ |
70 |
| - return *(TYPE *)&res; \ |
71 |
| - case Acquire: { \ |
72 |
| - __spirv_MemoryBarrier(scope, Acquire); \ |
73 |
| - return *(TYPE *)&res; \ |
74 |
| - } \ |
75 |
| - } \ |
76 |
| - } \ |
77 |
| - __builtin_trap(); \ |
78 |
| - __builtin_unreachable(); \ |
79 |
| - } |
80 |
| - |
81 |
| -#define __CLC_NVVM_ATOMIC_LOAD(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \ |
82 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \ |
83 |
| - __global, PU3AS1, _global_) \ |
84 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \ |
85 |
| - __local, PU3AS3, _shared_) \ |
86 |
| - __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, , \ |
87 |
| - P, _gen_) |
88 |
| - |
89 |
| -__CLC_NVVM_ATOMIC_LOAD(int, i, int, i) |
90 |
| -__CLC_NVVM_ATOMIC_LOAD(uint, j, int, i) |
91 |
| -__CLC_NVVM_ATOMIC_LOAD(long, l, long, l) |
92 |
| -__CLC_NVVM_ATOMIC_LOAD(ulong, m, long, l) |
93 |
| - |
94 |
| -__CLC_NVVM_ATOMIC_LOAD(float, f, float, f) |
95 |
| -#ifdef cl_khr_int64_base_atomics |
96 |
| -__CLC_NVVM_ATOMIC_LOAD(double, d, double, d) |
97 |
| -#endif |
98 |
| - |
99 |
| -#undef __CLC_NVVM_ATOMIC_LOAD_TYPES |
100 |
| -#undef __CLC_NVVM_ATOMIC_LOAD |
101 |
| -#undef __CLC_NVVM_ATOMIC_LOAD_IMPL |
| 1 | +//===----------------------------------------------------------------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | + |
| 9 | +#include <atomic_helpers.h> |
| 10 | +#include <libspirv/spirv.h> |
| 11 | +#include <libspirv/spirv_types.h> |
| 12 | + |
| 13 | +extern int __clc_nvvm_reflect_arch(); |
| 14 | +_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int); |
| 15 | + |
| 16 | +#define __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
| 17 | + ADDR_SPACE, ADDR_SPACE_NV, ORDER) \ |
| 18 | + switch (scope) { \ |
| 19 | + case Invocation: \ |
| 20 | + case Subgroup: \ |
| 21 | + case Workgroup: { \ |
| 22 | + TYPE_NV res = __nvvm##ORDER##_cta_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
| 23 | + (ADDR_SPACE TYPE_NV *)pointer); \ |
| 24 | + return *(TYPE *)&res; \ |
| 25 | + } \ |
| 26 | + case Device: { \ |
| 27 | + TYPE_NV res = __nvvm##ORDER##_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
| 28 | + (ADDR_SPACE TYPE_NV *)pointer); \ |
| 29 | + return *(TYPE *)&res; \ |
| 30 | + } \ |
| 31 | + case CrossDevice: \ |
| 32 | + default: { \ |
| 33 | + TYPE_NV res = __nvvm##ORDER##_sys_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
| 34 | + (ADDR_SPACE TYPE_NV *)pointer); \ |
| 35 | + return *(TYPE *)&res; \ |
| 36 | + } \ |
| 37 | + } |
| 38 | + |
| 39 | +#define __CLC_NVVM_ATOMIC_LOAD_IMPL( \ |
| 40 | + TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, ADDR_SPACE, \ |
| 41 | + POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \ |
| 42 | + __attribute__((always_inline)) _CLC_DECL TYPE _Z18__spirv_\ |
| 43 | +AtomicLoad##POINTER_AND_ADDR_SPACE_MANGLED##K##TYPE_MANGLED##N5__spv5\ |
| 44 | +Scope4FlagENS1_19MemorySemanticsMask4FlagE( \ |
| 45 | + const volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \ |
| 46 | + enum MemorySemanticsMask semantics) { \ |
| 47 | + /* Semantics mask may include memory order, storage class and other info \ |
| 48 | +Memory order is stored in the lowest 5 bits */ \ |
| 49 | + unsigned int order = semantics & 0x1F; \ |
| 50 | + if (__clc_nvvm_reflect_arch() >= 700) { \ |
| 51 | + switch (order) { \ |
| 52 | + case None: \ |
| 53 | + __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
| 54 | + ADDR_SPACE, ADDR_SPACE_NV, ) \ |
| 55 | + case Acquire: \ |
| 56 | + __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
| 57 | + ADDR_SPACE, ADDR_SPACE_NV, _acquire) \ |
| 58 | + break; \ |
| 59 | + case SequentiallyConsistent: \ |
| 60 | + __CLC_NVVM_FENCE_SC_SM70() \ |
| 61 | + __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \ |
| 62 | + ADDR_SPACE, ADDR_SPACE_NV, _acquire) \ |
| 63 | + break; \ |
| 64 | + } \ |
| 65 | + } else { \ |
| 66 | + TYPE_NV res = __nvvm_volatile_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \ |
| 67 | + (ADDR_SPACE TYPE_NV *)pointer); \ |
| 68 | + switch (order) { \ |
| 69 | + case None: \ |
| 70 | + return *(TYPE *)&res; \ |
| 71 | + case Acquire: { \ |
| 72 | + __spirv_MemoryBarrier(scope, Acquire); \ |
| 73 | + return *(TYPE *)&res; \ |
| 74 | + } \ |
| 75 | + } \ |
| 76 | + } \ |
| 77 | + __builtin_trap(); \ |
| 78 | + __builtin_unreachable(); \ |
| 79 | + } |
| 80 | + |
| 81 | +#define __CLC_NVVM_ATOMIC_LOAD(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \ |
| 82 | + __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \ |
| 83 | + __global, PU3AS1, _global_) \ |
| 84 | + __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \ |
| 85 | + __local, PU3AS3, _shared_) \ |
| 86 | + __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, , \ |
| 87 | + P, _gen_) |
| 88 | + |
| 89 | +__CLC_NVVM_ATOMIC_LOAD(int, i, int, i) |
| 90 | +__CLC_NVVM_ATOMIC_LOAD(uint, j, int, i) |
| 91 | +__CLC_NVVM_ATOMIC_LOAD(long, l, long, l) |
| 92 | +__CLC_NVVM_ATOMIC_LOAD(ulong, m, long, l) |
| 93 | + |
| 94 | +__CLC_NVVM_ATOMIC_LOAD(float, f, float, f) |
| 95 | +#ifdef cl_khr_int64_base_atomics |
| 96 | +__CLC_NVVM_ATOMIC_LOAD(double, d, double, d) |
| 97 | +#endif |
| 98 | + |
| 99 | +#undef __CLC_NVVM_ATOMIC_LOAD_TYPES |
| 100 | +#undef __CLC_NVVM_ATOMIC_LOAD |
| 101 | +#undef __CLC_NVVM_ATOMIC_LOAD_IMPL |
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