Merge from 'main' to 'sycl-web' (354 commits)

  CONFLICT (content): Merge conflict in clang/lib/Driver/Types.cpp

Author: smanna12

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -282,6 +282,8 @@ class MCPlusBuilder {
     // Initialize the default annotation allocator with id 0
     AnnotationAllocators.emplace(0, AnnotationAllocator());
     MaxAllocatorId++;
+    // Build alias map
+    initAliases();
   }
 
   /// Initialize a new annotation allocator and return its id
@@ -1135,6 +1137,9 @@ class MCPlusBuilder {
   virtual const BitVector &getAliases(MCPhysReg Reg,
                                       bool OnlySmaller = false) const;
 
+  /// Initialize aliases tables.
+  virtual void initAliases();
+
   /// Change \p Regs setting all registers used to pass parameters according
   /// to the host abi. Do nothing if not implemented.
   virtual BitVector getRegsUsedAsParams() const {
@@ -1904,6 +1909,11 @@ class MCPlusBuilder {
     llvm_unreachable("not implemented");
     return BlocksVectorTy();
   }
+
+  // AliasMap caches a mapping of registers to the set of registers that
+  // alias (are sub or superregs of itself, including itself).
+  std::vector<BitVector> AliasMap;
+  std::vector<BitVector> SmallerAliasMap;
 };
 
 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *,

bolt/include/bolt/Passes/Inliner.h

@@ -18,22 +18,24 @@
 namespace llvm {
 namespace bolt {
 
-class Inliner : public BinaryFunctionPass {
-private:
-  enum InliningType : char {
-    INL_NONE = 0, /// Cannot inline
-    INL_TAILCALL, /// Can inline at tail call site
-    INL_ANY       /// Can inline at any call site
-  };
+enum InliningType : char {
+  INL_NONE = 0, /// Cannot inline
+  INL_TAILCALL, /// Can inline at tail call site
+  INL_ANY       /// Can inline at any call site
+};
+
+struct InliningInfo {
+  InliningType Type{INL_NONE};
+  uint64_t SizeAfterInlining{0};
+  uint64_t SizeAfterTailCallInlining{0};
 
-  struct InliningInfo {
-    InliningType Type{INL_NONE};
-    uint64_t SizeAfterInlining{0};
-    uint64_t SizeAfterTailCallInlining{0};
+  InliningInfo(InliningType Type = INL_NONE) : Type(Type) {}
+};
 
-    InliningInfo(InliningType Type = INL_NONE) : Type(Type) {}
-  };
+/// Check if the inliner can handle inlining of \p BF.
+InliningInfo getInliningInfo(const BinaryFunction &BF);
 
+class Inliner : public BinaryFunctionPass {
   std::unordered_map<const BinaryFunction *, InliningInfo> InliningCandidates;
 
   /// Count total amount of bytes inlined for all instances of Inliner.
@@ -74,9 +76,6 @@ class Inliner : public BinaryFunctionPass {
   inlineCall(BinaryBasicBlock &CallerBB, BinaryBasicBlock::iterator CallInst,
              const BinaryFunction &Callee);
 
-  /// Check if the inliner can handle inlining of \p BF.
-  InliningInfo getInliningInfo(const BinaryFunction &BF) const;
-
 public:
   explicit Inliner(const cl::opt<bool> &PrintPass)
       : BinaryFunctionPass(PrintPass) {}

bolt/lib/Core/BinaryFunctionProfile.cpp

@@ -27,17 +27,16 @@ namespace opts {
 
 extern cl::OptionCategory BoltOptCategory;
 
-cl::opt<IndirectCallPromotionType>
-IndirectCallPromotion("indirect-call-promotion",
-  cl::init(ICP_NONE),
-  cl::desc("indirect call promotion"),
-  cl::values(
-    clEnumValN(ICP_NONE, "none", "do not perform indirect call promotion"),
-    clEnumValN(ICP_CALLS, "calls", "perform ICP on indirect calls"),
-    clEnumValN(ICP_JUMP_TABLES, "jump-tables", "perform ICP on jump tables"),
-    clEnumValN(ICP_ALL, "all", "perform ICP on calls and jump tables")),
-  cl::ZeroOrMore,
-  cl::cat(BoltOptCategory));
+cl::opt<IndirectCallPromotionType> ICP(
+    "indirect-call-promotion", cl::init(ICP_NONE),
+    cl::desc("indirect call promotion"),
+    cl::values(
+        clEnumValN(ICP_NONE, "none", "do not perform indirect call promotion"),
+        clEnumValN(ICP_CALLS, "calls", "perform ICP on indirect calls"),
+        clEnumValN(ICP_JUMP_TABLES, "jump-tables",
+                   "perform ICP on jump tables"),
+        clEnumValN(ICP_ALL, "all", "perform ICP on calls and jump tables")),
+    cl::ZeroOrMore, cl::cat(BoltOptCategory));
 
 extern cl::opt<JumpTableSupportLevel> JumpTables;
 
@@ -173,8 +172,7 @@ void BinaryFunction::postProcessProfile() {
     }
     JT->Count += TotalBranchCount;
 
-    if (opts::IndirectCallPromotion < ICP_JUMP_TABLES &&
-        opts::JumpTables < JTS_AGGRESSIVE)
+    if (opts::ICP < ICP_JUMP_TABLES && opts::JumpTables < JTS_AGGRESSIVE)
       continue;
 
     if (JT->Counts.empty())

bolt/lib/Core/MCPlusBuilder.cpp

@@ -441,17 +441,13 @@ bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
 
 const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
                                            bool OnlySmaller) const {
-  // AliasMap caches a mapping of registers to the set of registers that
-  // alias (are sub or superregs of itself, including itself).
-  static std::vector<BitVector> AliasMap;
-  static std::vector<BitVector> SmallerAliasMap;
-
-  if (AliasMap.size() > 0) {
-    if (OnlySmaller)
-      return SmallerAliasMap[Reg];
-    return AliasMap[Reg];
-  }
+  if (OnlySmaller)
+    return SmallerAliasMap[Reg];
+  return AliasMap[Reg];
+}
 
+void MCPlusBuilder::initAliases() {
+  assert(AliasMap.size() == 0 && SmallerAliasMap.size() == 0);
   // Build alias map
   for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
     BitVector BV(RegInfo->getNumRegs(), false);
@@ -492,10 +488,6 @@ const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
       dbgs() << "\n";
     }
   });
-
-  if (OnlySmaller)
-    return SmallerAliasMap[Reg];
-  return AliasMap[Reg];
 }
 
 uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const {