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Add 'convergent' attribute for group and subgroup instructions.
Signed-off-by: Alexey Sotkin <alexey.sotkin@intel.com>
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‎llvm-spirv/lib/SPIRV/SPIRVReader.cpp

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@@ -3262,6 +3262,9 @@ Instruction *SPIRVToLLVM::transBuiltinFromInst(const std::string &FuncName,
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Func->setCallingConv(CallingConv::SPIR_FUNC);
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if (isFuncNoUnwind())
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Func->addFnAttr(Attribute::NoUnwind);
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auto OC = BI->getOpCode();
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if (isGroupOpCode(OC) || isIntelSubgroupOpCode(OC))
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Func->addFnAttr(Attribute::Convergent);
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}
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auto Call =
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CallInst::Create(Func, transValue(Ops, BB->getParent(), BB), "", BB);

‎llvm-spirv/test/GroupAndSubgroupInstructions.spvasm

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; Generated with:
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; source.cl:
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; void foo(int x, int2 coord, uint c, short s, float f, size_t n,
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; __global uint* p, read_write image2d_t image) {
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; work_group_all(x);
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; work_group_any(x);
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; work_group_broadcast(x, n);
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; sub_group_barrier(CLK_LOCAL_MEM_FENCE, memory_scope_sub_group);
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; sub_group_all(x);
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; sub_group_any(x);
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; sub_group_broadcast(x, c);
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; sub_group_reduce_add(x);
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; sub_group_reduce_add(f);
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; sub_group_reduce_min(x);
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; sub_group_reduce_min(c);
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; sub_group_reduce_min(f);
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; sub_group_reduce_max(x);
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; sub_group_reduce_max(c);
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; sub_group_reduce_max(f);
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; intel_sub_group_shuffle(x, c);
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; intel_sub_group_shuffle_down(x, x, c);
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; intel_sub_group_shuffle_up(x, x, c);
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; intel_sub_group_shuffle_xor(x, c);
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; intel_sub_group_block_read(p);
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; intel_sub_group_block_write(p, c);
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; intel_sub_group_block_read(image, coord);
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; intel_sub_group_block_write(image, coord, c);
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; }
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; clang -cc1 -O2 -triple spir -cl-std=cl2.0 -finclude-default-header -cl-ext=+all source.cl -emit-llvm-bc -o tmp.bc
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; llvm-spirv tmp.bc --spirv-ext=+all -o tmp.spv
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; spirv-dis tmp.spv -o llvm-spirv/test/GroupAndSubgroupInstructions.spvasm
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; REQUIRES: spirv-as
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; RUN: spirv-as < %s --target-env spv1.0 -o %t.spv
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; RUN: spirv-val %t.spv
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; RUN: llvm-spirv -r %t.spv --spirv-target-env=CL1.2 -o %t.bc
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; RUN: llvm-dis %t.bc -o %t.ll
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; RUN: FileCheck < %t.ll %s --check-prefixes=CHECK-COMMON,CHECK-CL,CHECK-CL12
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; RUN: llvm-spirv -r %t.spv --spirv-target-env=CL2.0 -o %t.bc
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; RUN: llvm-dis %t.bc -o %t.ll
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; RUN: FileCheck < %t.ll %s --check-prefixes=CHECK-COMMON,CHECK-CL,CHECK-CL20
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; RUN: llvm-spirv -r %t.spv --spirv-target-env=SPV-IR -o %t.bc
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; RUN: llvm-dis %t.bc -o %t.ll
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; RUN: FileCheck < %t.ll %s --check-prefixes=CHECK-COMMON,CHECK-SPV-IR
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; CHECK-CL-DAG: declare spir_func i32 @_Z14work_group_alli(i32) #[[#Attrs:]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z14work_group_anyi(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20work_group_broadcastjj(i32, i32) #[[#Attrs]]
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; CHECK-CL12-DAG: declare spir_func void @_Z7barrierj(i32) #[[#Attrs]]
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; CHECK-CL20-DAG: declare spir_func void @_Z17sub_group_barrierj12memory_scope(i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z13sub_group_alli(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z13sub_group_anyi(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z19sub_group_broadcastjj(i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20sub_group_reduce_addi(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func float @_Z20sub_group_reduce_addf(float) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20sub_group_reduce_mini(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20sub_group_reduce_minj(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func float @_Z20sub_group_reduce_minf(float) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20sub_group_reduce_maxi(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z20sub_group_reduce_maxj(i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func float @_Z20sub_group_reduce_maxf(float) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z23intel_sub_group_shuffleij(i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z28intel_sub_group_shuffle_downiij(i32, i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z26intel_sub_group_shuffle_upiij(i32, i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z27intel_sub_group_shuffle_xorij(i32, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z26intel_sub_group_block_readPU3AS1Kj(i32 addrspace(1)*) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func void @_Z27intel_sub_group_block_writePU3AS1jj(i32 addrspace(1)*, i32) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func i32 @_Z26intel_sub_group_block_read14ocl_image2d_rwDv2_i(%opencl.image2d_rw_t addrspace(1)*, <2 x i32>) #[[#Attrs]]
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; CHECK-CL-DAG: declare spir_func void @_Z27intel_sub_group_block_write14ocl_image2d_rwDv2_ij(%opencl.image2d_rw_t addrspace(1)*, <2 x i32>, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i1 @_Z16__spirv_GroupAllib(i32, i1) #[[#Attrs:]]
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; CHECK-SPV-IR: declare spir_func i1 @_Z16__spirv_GroupAnyib(i32, i1) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z22__spirv_GroupBroadcastiii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func void @_Z22__spirv_ControlBarrieriii(i32, i32, i32) #0
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; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupIAddiii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFAddiif(i32, i32, float) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupSMiniii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMiniii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFMiniif(i32, i32, float) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupSMaxiii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMaxiii(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFMaxiif(i32, i32, float) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z23intel_sub_group_shuffleij(i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z28intel_sub_group_shuffle_downiij(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z26intel_sub_group_shuffle_upiij(i32, i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z27intel_sub_group_shuffle_xorij(i32, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z26intel_sub_group_block_readPU3AS1Kj(i32 addrspace(1)*) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func void @_Z27intel_sub_group_block_writePU3AS1jj(i32 addrspace(1)*, i32) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func i32 @_Z26intel_sub_group_block_read14ocl_image2d_rwDv2_i(%opencl.image2d_rw_t addrspace(1)*, <2 x i32>) #[[#Attrs]]
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; CHECK-SPV-IR: declare spir_func void @_Z27intel_sub_group_block_write14ocl_image2d_rwDv2_ij(%opencl.image2d_rw_t addrspace(1)*, <2 x i32>, i32) #[[#Attrs]]
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; CHECK-COMMON: attributes #[[#Attrs]] =
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; CHECK-COMMON-SAME: convergent
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; SPIR-V
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; Version: 1.0
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; Generator: Khronos LLVM/SPIR-V Translator; 14
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; Bound: 60
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; Schema: 0
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OpCapability Addresses
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OpCapability Linkage
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OpCapability Kernel
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OpCapability ImageBasic
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OpCapability ImageReadWrite
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OpCapability Groups
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OpCapability Int16
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OpCapability GenericPointer
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OpCapability SubgroupShuffleINTEL
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OpCapability SubgroupBufferBlockIOINTEL
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OpCapability SubgroupImageBlockIOINTEL
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OpExtension "SPV_INTEL_subgroups"
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%1 = OpExtInstImport "OpenCL.std"
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OpMemoryModel Physical32 OpenCL
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OpSource OpenCL_C 200000
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OpDecorate %s FuncParamAttr Sext
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OpDecorate %dst FuncParamAttr NoCapture
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OpDecorate %src FuncParamAttr NoCapture
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OpDecorate %e FuncParamAttr NoCapture
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OpDecorate %foo LinkageAttributes "foo" Export
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%uint = OpTypeInt 32 0
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%ushort = OpTypeInt 16 0
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%uint_0 = OpConstant %uint 0
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%uint_2 = OpConstant %uint 2
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%uint_1 = OpConstant %uint 1
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%uint_3 = OpConstant %uint 3
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%uint_272 = OpConstant %uint 272
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%void = OpTypeVoid
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%v2uint = OpTypeVector %uint 2
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%float = OpTypeFloat 32
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%_ptr_CrossWorkgroup_uint = OpTypePointer CrossWorkgroup %uint
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%_ptr_Workgroup_uint = OpTypePointer Workgroup %uint
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%Event = OpTypeEvent
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%_ptr_Generic_Event = OpTypePointer Generic %Event
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%11 = OpTypeImage %void 2D 0 0 0 0 Unknown ReadWrite
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%12 = OpTypeFunction %void %uint %v2uint %uint %ushort %float %uint %_ptr_CrossWorkgroup_uint %_ptr_Workgroup_uint %_ptr_CrossWorkgroup_uint %_ptr_Generic_Event %11
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%bool = OpTypeBool
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%foo = OpFunction %void None %12
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%x = OpFunctionParameter %uint
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%coord = OpFunctionParameter %v2uint
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%c = OpFunctionParameter %uint
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%s = OpFunctionParameter %ushort
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%f = OpFunctionParameter %float
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%n = OpFunctionParameter %uint
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%p = OpFunctionParameter %_ptr_CrossWorkgroup_uint
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%dst = OpFunctionParameter %_ptr_Workgroup_uint
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%src = OpFunctionParameter %_ptr_CrossWorkgroup_uint
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%e = OpFunctionParameter %_ptr_Generic_Event
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%image = OpFunctionParameter %11
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%entry = OpLabel
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%28 = OpINotEqual %bool %x %uint_0
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%call20 = OpGroupAll %bool %uint_2 %28
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%call = OpSelect %uint %call20 %uint_1 %uint_0
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%33 = OpINotEqual %bool %x %uint_0
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%call121 = OpGroupAny %bool %uint_2 %33
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%call1 = OpSelect %uint %call121 %uint_1 %uint_0
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%call2 = OpGroupBroadcast %uint %uint_2 %x %n
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OpControlBarrier %uint_3 %uint_3 %uint_272
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%39 = OpINotEqual %bool %x %uint_0
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%call322 = OpGroupAll %bool %uint_3 %39
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%call3 = OpSelect %uint %call322 %uint_1 %uint_0
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%42 = OpINotEqual %bool %x %uint_0
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%call423 = OpGroupAny %bool %uint_3 %42
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%call4 = OpSelect %uint %call423 %uint_1 %uint_0
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%call5 = OpGroupBroadcast %uint %uint_3 %x %c
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%call6 = OpGroupIAdd %uint %uint_3 Reduce %x
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%call7 = OpGroupFAdd %float %uint_3 Reduce %f
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%call8 = OpGroupSMin %uint %uint_3 Reduce %x
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%call9 = OpGroupUMin %uint %uint_3 Reduce %c
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%call10 = OpGroupFMin %float %uint_3 Reduce %f
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%call11 = OpGroupSMax %uint %uint_3 Reduce %x
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%call12 = OpGroupUMax %uint %uint_3 Reduce %c
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%call13 = OpGroupFMax %float %uint_3 Reduce %f
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%call14 = OpSubgroupShuffleINTEL %uint %x %c
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%call15 = OpSubgroupShuffleDownINTEL %uint %x %x %c
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%call16 = OpSubgroupShuffleUpINTEL %uint %x %x %c
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%call17 = OpSubgroupShuffleXorINTEL %uint %x %c
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%call18 = OpSubgroupBlockReadINTEL %uint %p
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OpSubgroupBlockWriteINTEL %p %c
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%call19 = OpSubgroupImageBlockReadINTEL %uint %image %coord
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OpSubgroupImageBlockWriteINTEL %image %coord %c
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OpReturn
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OpFunctionEnd

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