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Krzysztof Parzyszek
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[Hexagon] Add instruction definitions for Hexagon v71, v71t, and v73
This includes instruction formats, definitions, encodings, scheduling classes, and builtins/intrinsics. New and improved version of 76536989ba, so much so that even clang builds with it.
1 parent 36991d8 commit a98fc08

26 files changed

+5689
-171
lines changed

‎clang/include/clang/Basic/BuiltinsHexagon.def

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,12 @@
1717
# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
1818
#endif
1919

20+
#pragma push_macro("V73")
21+
#define V73 "v73"
22+
#pragma push_macro("V71")
23+
#define V71 "v71|" V73
2024
#pragma push_macro("V69")
21-
#define V69 "v69"
25+
#define V69 "v69|" V71
2226
#pragma push_macro("V68")
2327
#define V68 "v68|" V69
2428
#pragma push_macro("V67")
@@ -36,8 +40,12 @@
3640
#pragma push_macro("V5")
3741
#define V5 "v5|" V55
3842

43+
#pragma push_macro("HVXV73")
44+
#define HVXV73 "hvxv73"
45+
#pragma push_macro("HVXV71")
46+
#define HVXV71 "hvxv71|" HVXV73
3947
#pragma push_macro("HVXV69")
40-
#define HVXV69 "hvxv69"
48+
#define HVXV69 "hvxv69|" HVXV71
4149
#pragma push_macro("HVXV68")
4250
#define HVXV68 "hvxv68|" HVXV69
4351
#pragma push_macro("HVXV67")
@@ -133,6 +141,8 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
133141
#pragma pop_macro("HVXV67")
134142
#pragma pop_macro("HVXV68")
135143
#pragma pop_macro("HVXV69")
144+
#pragma pop_macro("HVXV71")
145+
#pragma pop_macro("HVXV73")
136146

137147
#pragma pop_macro("V5")
138148
#pragma pop_macro("V55")
@@ -143,6 +153,8 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
143153
#pragma pop_macro("V67")
144154
#pragma pop_macro("V68")
145155
#pragma pop_macro("V69")
156+
#pragma pop_macro("V71")
157+
#pragma pop_macro("V73")
146158

147159
#undef BUILTIN
148160
#undef TARGET_BUILTIN

‎clang/include/clang/Basic/BuiltinsHexagonDep.def

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1890,3 +1890,36 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat, "V16iV32iV16i", "", HVXV69)
18901890
TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat_128B, "V32iV64iV32i", "", HVXV69)
18911891
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs, "V16iV16iV16i", "", HVXV69)
18921892
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs_128B, "V32iV32iV32i", "", HVXV69)
1893+
1894+
// V73 HVX Instructions.
1895+
1896+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf, "V32iV16iV16i", "", HVXV73)
1897+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
1898+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf, "V16iV16i", "", HVXV73)
1899+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf_128B, "V32iV32i", "", HVXV73)
1900+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h, "V16iV16i", "", HVXV73)
1901+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h_128B, "V32iV32i", "", HVXV73)
1902+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w, "V16iV16i", "", HVXV73)
1903+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w_128B, "V32iV32i", "", HVXV73)
1904+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf, "V16iV16i", "", HVXV73)
1905+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf_128B, "V32iV32i", "", HVXV73)
1906+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf, "V16iV16iV16i", "", HVXV73)
1907+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf_128B, "V32iV32iV32i", "", HVXV73)
1908+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf, "V64bV16iV16i", "", HVXV73)
1909+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_128B, "V128bV32iV32i", "", HVXV73)
1910+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and, "V64bV64bV16iV16i", "", HVXV73)
1911+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and_128B, "V128bV128bV32iV32i", "", HVXV73)
1912+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or, "V64bV64bV16iV16i", "", HVXV73)
1913+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or_128B, "V128bV128bV32iV32i", "", HVXV73)
1914+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor, "V64bV64bV16iV16i", "", HVXV73)
1915+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor_128B, "V128bV128bV32iV32i", "", HVXV73)
1916+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf, "V16iV16iV16i", "", HVXV73)
1917+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf_128B, "V32iV32iV32i", "", HVXV73)
1918+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf, "V16iV16iV16i", "", HVXV73)
1919+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf_128B, "V32iV32iV32i", "", HVXV73)
1920+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf, "V32iV16iV16i", "", HVXV73)
1921+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
1922+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc, "V32iV32iV16iV16i", "", HVXV73)
1923+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B, "V64iV64iV32iV32i", "", HVXV73)
1924+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf, "V32iV16iV16i", "", HVXV73)
1925+
TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf_128B, "V64iV32iV32i", "", HVXV73)

‎llvm/include/llvm/IR/IntrinsicsHexagonDep.td

Lines changed: 95 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix,
316316
[llvm_v32i32_ty], [llvm_v64i32_ty],
317317
intr_properties>;
318318

319-
// tag : V6_lvsplatw
319+
// tag : V6_lvsplatb
320320
class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix,
321321
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
322322
: Hexagon_Intrinsic<GCCIntSuffix,
@@ -442,14 +442,14 @@ class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
442442
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
443443
intr_properties>;
444444

445-
// tag : V6_vadd_sf_hf
445+
// tag : V6_vadd_sf_bf
446446
class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,
447447
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
448448
: Hexagon_Intrinsic<GCCIntSuffix,
449449
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
450450
intr_properties>;
451451

452-
// tag : V6_vadd_sf_hf
452+
// tag : V6_vadd_sf_bf
453453
class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
454454
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
455455
: Hexagon_Intrinsic<GCCIntSuffix,
@@ -6613,3 +6613,95 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhvs">;
66136613
def int_hexagon_V6_vmpyuhvs_128B :
66146614
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhvs_128B">;
66156615

6616+
// V73 HVX Instructions.
6617+
6618+
def int_hexagon_V6_vadd_sf_bf :
6619+
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf">;
6620+
6621+
def int_hexagon_V6_vadd_sf_bf_128B :
6622+
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf_128B">;
6623+
6624+
def int_hexagon_V6_vconv_h_hf :
6625+
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_h_hf">;
6626+
6627+
def int_hexagon_V6_vconv_h_hf_128B :
6628+
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_h_hf_128B">;
6629+
6630+
def int_hexagon_V6_vconv_hf_h :
6631+
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_h">;
6632+
6633+
def int_hexagon_V6_vconv_hf_h_128B :
6634+
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_h_128B">;
6635+
6636+
def int_hexagon_V6_vconv_sf_w :
6637+
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_w">;
6638+
6639+
def int_hexagon_V6_vconv_sf_w_128B :
6640+
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_w_128B">;
6641+
6642+
def int_hexagon_V6_vconv_w_sf :
6643+
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_w_sf">;
6644+
6645+
def int_hexagon_V6_vconv_w_sf_128B :
6646+
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_w_sf_128B">;
6647+
6648+
def int_hexagon_V6_vcvt_bf_sf :
6649+
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf">;
6650+
6651+
def int_hexagon_V6_vcvt_bf_sf_128B :
6652+
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf_128B">;
6653+
6654+
def int_hexagon_V6_vgtbf :
6655+
Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf">;
6656+
6657+
def int_hexagon_V6_vgtbf_128B :
6658+
Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_128B">;
6659+
6660+
def int_hexagon_V6_vgtbf_and :
6661+
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_and">;
6662+
6663+
def int_hexagon_V6_vgtbf_and_128B :
6664+
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_and_128B">;
6665+
6666+
def int_hexagon_V6_vgtbf_or :
6667+
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_or">;
6668+
6669+
def int_hexagon_V6_vgtbf_or_128B :
6670+
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_or_128B">;
6671+
6672+
def int_hexagon_V6_vgtbf_xor :
6673+
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_xor">;
6674+
6675+
def int_hexagon_V6_vgtbf_xor_128B :
6676+
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_xor_128B">;
6677+
6678+
def int_hexagon_V6_vmax_bf :
6679+
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_bf">;
6680+
6681+
def int_hexagon_V6_vmax_bf_128B :
6682+
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_bf_128B">;
6683+
6684+
def int_hexagon_V6_vmin_bf :
6685+
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_bf">;
6686+
6687+
def int_hexagon_V6_vmin_bf_128B :
6688+
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_bf_128B">;
6689+
6690+
def int_hexagon_V6_vmpy_sf_bf :
6691+
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf">;
6692+
6693+
def int_hexagon_V6_vmpy_sf_bf_128B :
6694+
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_128B">;
6695+
6696+
def int_hexagon_V6_vmpy_sf_bf_acc :
6697+
Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc">;
6698+
6699+
def int_hexagon_V6_vmpy_sf_bf_acc_128B :
6700+
Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc_128B">;
6701+
6702+
def int_hexagon_V6_vsub_sf_bf :
6703+
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf">;
6704+
6705+
def int_hexagon_V6_vsub_sf_bf_128B :
6706+
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf_128B">;
6707+

‎llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -354,6 +354,11 @@ struct HexagonOperand : public MCParsedAsmOperand {
354354
return false;
355355
return Value == -1;
356356
}
357+
bool issgp10Const() const {
358+
if (!isReg())
359+
return false;
360+
return getReg() == Hexagon::SGP1_0;
361+
}
357362
bool iss11_0Imm() const {
358363
return CheckImmRange(11 + 26, 0, true, true, true);
359364
}
@@ -400,6 +405,9 @@ struct HexagonOperand : public MCParsedAsmOperand {
400405
void addn1ConstOperands(MCInst &Inst, unsigned N) const {
401406
addImmOperands(Inst, N);
402407
}
408+
void addsgp10ConstOperands(MCInst &Inst, unsigned N) const {
409+
addRegOperands(Inst, N);
410+
}
403411

404412
StringRef getToken() const {
405413
assert(Kind == Token && "Invalid access!");

‎llvm/lib/Target/Hexagon/Hexagon.td

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,14 @@ def ExtensionHVXV69: SubtargetFeature<"hvxv69", "HexagonHVXVersion",
5858
"Hexagon::ArchEnum::V69", "Hexagon HVX instructions",
5959
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
6060
ExtensionHVXV67, ExtensionHVXV68]>;
61+
def ExtensionHVXV71: SubtargetFeature<"hvxv71", "HexagonHVXVersion",
62+
"Hexagon::ArchEnum::V71", "Hexagon HVX instructions",
63+
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
64+
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69]>;
65+
def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",
66+
"Hexagon::ArchEnum::V73", "Hexagon HVX instructions",
67+
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
68+
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;
6169

6270
def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
6371
"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
@@ -125,6 +133,10 @@ def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">,
125133
AssemblerPredicate<(all_of ExtensionHVXV68)>;
126134
def UseHVXV69 : Predicate<"HST->useHVXV69Ops()">,
127135
AssemblerPredicate<(all_of ExtensionHVXV69)>;
136+
def UseHVXV71 : Predicate<"HST->useHVXV71Ops()">,
137+
AssemblerPredicate<(all_of ExtensionHVXV71)>;
138+
def UseHVXV73 : Predicate<"HST->useHVXV73Ops()">,
139+
AssemblerPredicate<(all_of ExtensionHVXV73)>;
128140
def UseAudio : Predicate<"HST->useAudioOps()">,
129141
AssemblerPredicate<(all_of ExtensionAudio)>;
130142
def UseZReg : Predicate<"HST->useZRegOps()">,
@@ -439,6 +451,17 @@ def : Proc<"hexagonv69", HexagonModelV69,
439451
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
440452
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
441453
FeatureCabac]>;
454+
def : Proc<"hexagonv71", HexagonModelV71,
455+
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
456+
ArchV68, ArchV69, ArchV71,
457+
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
458+
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
459+
FeatureCabac]>;
460+
def : Proc<"hexagonv73", HexagonModelV73,
461+
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
462+
ArchV68, ArchV69, ArchV71, ArchV73,
463+
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
464+
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
442465
// Need to update the correct features for tiny core.
443466
// Disable NewValueJumps since the packetizer is unable to handle a packet with
444467
// a new value jump and another SLOT0 instruction.
@@ -448,6 +471,13 @@ def : Proc<"hexagonv67t", HexagonModelV67T,
448471
FeatureCompound, FeatureMemNoShuf, FeatureMemops,
449472
FeatureNVS, FeaturePackets, FeatureSmallData]>;
450473

474+
def : Proc<"hexagonv71t", HexagonModelV71T,
475+
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
476+
ArchV68, ArchV69, ArchV71,
477+
ProcTinyCore, ExtensionAudio,
478+
FeatureCompound, FeatureMemNoShuf, FeatureMemops,
479+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
480+
451481
//===----------------------------------------------------------------------===//
452482
// Declare the target which we are implementing
453483
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Hexagon/HexagonDepArch.h

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,6 @@
55
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
//
77
//===----------------------------------------------------------------------===//
8-
// Automatically generated file, do not edit!
9-
//===----------------------------------------------------------------------===//
10-
118

129
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
1310
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
@@ -16,7 +13,21 @@
1613

1714
namespace llvm {
1815
namespace Hexagon {
19-
enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68, V69 };
16+
enum class ArchEnum {
17+
NoArch,
18+
Generic,
19+
V5,
20+
V55,
21+
V60,
22+
V62,
23+
V65,
24+
V66,
25+
V67,
26+
V68,
27+
V69,
28+
V71,
29+
V73
30+
};
2031

2132
inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
2233
return StringSwitch<Optional<Hexagon::ArchEnum>>(CPU)
@@ -31,6 +42,9 @@ inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
3142
.Case("hexagonv67t", Hexagon::ArchEnum::V67)
3243
.Case("hexagonv68", Hexagon::ArchEnum::V68)
3344
.Case("hexagonv69", Hexagon::ArchEnum::V69)
45+
.Case("hexagonv71", Hexagon::ArchEnum::V71)
46+
.Case("hexagonv71t", Hexagon::ArchEnum::V71)
47+
.Case("hexagonv73", Hexagon::ArchEnum::V73)
3448
.Default(None);
3549
}
3650
} // namespace Hexagon

‎llvm/lib/Target/Hexagon/HexagonDepArch.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,7 @@ def ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V
2626
def HasV68 : Predicate<"HST->hasV68Ops()">, AssemblerPredicate<(all_of ArchV68)>;
2727
def ArchV69: SubtargetFeature<"v69", "HexagonArchVersion", "Hexagon::ArchEnum::V69", "Enable Hexagon V69 architecture">;
2828
def HasV69 : Predicate<"HST->hasV69Ops()">, AssemblerPredicate<(all_of ArchV69)>;
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def ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V71", "Enable Hexagon V71 architecture">;
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def HasV71 : Predicate<"HST->hasV71Ops()">, AssemblerPredicate<(all_of ArchV71)>;
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def ArchV73: SubtargetFeature<"v73", "HexagonArchVersion", "Hexagon::ArchEnum::V73", "Enable Hexagon V73 architecture">;
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def HasV73 : Predicate<"HST->hasV73Ops()">, AssemblerPredicate<(all_of ArchV73)>;

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