LLVM and SPIRV-LLVM-Translator pulldown (WW18)

LLVM: llvm/llvm-project@483efc9
SPIRV-LLVM-Translator: KhronosGroup/SPIRV-LLVM-Translator@28fdb7a

Author: bb-sycl

bolt/CMakeLists.txt

@@ -59,28 +59,7 @@ if (BOLT_ENABLE_RUNTIME)
     COMPONENT bolt)
 endif()
 
-# Get the current git revision for BOLT.
-find_program(git_executable NAMES git git.exe git.cmd)
-if (git_executable)
-  execute_process(COMMAND ${git_executable} rev-parse HEAD
-    WORKING_DIRECTORY ${LLVM_MAIN_SRC_DIR}
-    TIMEOUT 5
-    RESULT_VARIABLE git_result
-    OUTPUT_VARIABLE git_output)
-  if( git_result EQUAL 0 )
-    string(STRIP "${git_output}" git_ref_id)
-    set(BOLT_REVISION "${git_ref_id}")
-  endif()
-endif()
-
-# If we can't find a revision, set it to "<unknown>".
-if (NOT BOLT_REVISION)
-  set(BOLT_REVISION "<unknown>")
-endif()
-
-configure_file(
-  ${CMAKE_CURRENT_SOURCE_DIR}/include/bolt/Utils/BoltRevision.inc.in
-  ${CMAKE_CURRENT_BINARY_DIR}/include/bolt/Utils/BoltRevision.inc)
+find_program(GNU_LD_EXECUTABLE NAMES ${LLVM_DEFAULT_TARGET_TRIPLE}-ld.bfd ld.bfd DOC "GNU ld")
 
 include_directories(
   ${CMAKE_CURRENT_SOURCE_DIR}/include

bolt/docs/Heatmaps.md

@@ -20,8 +20,10 @@ or if you want to monitor the existing process(es):
 $ perf record -e cycles:u -j any,u [-p PID|-a] -- sleep <interval>
 ```
 
-Note that at the moment running with LBR (`-j any,u` or `-b`) is
-a requirement.
+Running with LBR (`-j any,u` or `-b`) is recommended. Heatmaps can be generated
+from basic events by using the llvm-bolt-heatmap option `-nl` (no LBR) but
+such heatmaps do not have the coverage provided by LBR and may only be useful
+for finding event hotspots at larger code block granularities.
 
 Once the run is complete, and `perf.data` is generated, run llvm-bolt-heatmap:
 

bolt/include/bolt/Core/BinaryContext.h

@@ -774,6 +774,22 @@ class BinaryContext {
     return Itr != GlobalSymbols.end() ? Itr->second : nullptr;
   }
 
+  /// Return registered PLT entry BinaryData with the given \p Name
+  /// or nullptr if no global PLT symbol with that name exists.
+  const BinaryData *getPLTBinaryDataByName(StringRef Name) const {
+    if (const BinaryData *Data = getBinaryDataByName(Name.str() + "@PLT"))
+      return Data;
+
+    // The symbol name might contain versioning information e.g
+    // memcpy@@GLIBC_2.17. Remove it and try to locate binary data
+    // without it.
+    size_t At = Name.find("@");
+    if (At != std::string::npos)
+      return getBinaryDataByName(Name.str().substr(0, At) + "@PLT");
+
+    return nullptr;
+  }
+
   /// Return true if \p SymbolName was generated internally and was not present
   /// in the input binary.
   bool isInternalSymbolName(const StringRef Name) {
@@ -954,6 +970,15 @@ class BinaryContext {
                                               Sections.end()));
   }
 
+  /// Return base address for the shared object or PIE based on the segment
+  /// mapping information. \p MMapAddress is an address where one of the
+  /// segments was mapped. \p FileOffset is the offset in the file of the
+  /// mapping. Note that \p FileOffset should be page-aligned and could be
+  /// different from the file offset of the segment which could be unaligned.
+  /// If no segment is found that matches \p FileOffset, return NoneType().
+  Optional<uint64_t> getBaseAddressForMapping(uint64_t MMapAddress,
+                                              uint64_t FileOffset) const;
+
   /// Check if the address belongs to this binary's static allocation space.
   bool containsAddress(uint64_t Address) const {
     return Address >= FirstAllocAddress && Address < LayoutStartAddress;

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -353,7 +353,7 @@ class MCPlusBuilder {
   }
 
   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
-    return Analysis->isUnconditionalBranch(Inst);
+    return Analysis->isUnconditionalBranch(Inst) && !isTailCall(Inst);
   }
 
   virtual bool isIndirectBranch(const MCInst &Inst) const {
@@ -511,11 +511,6 @@ class MCPlusBuilder {
     return 0;
   }
 
-  virtual bool isADD64rr(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
-
   virtual bool isSUB(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;

bolt/include/bolt/Profile/DataAggregator.h

@@ -168,14 +168,15 @@ class DataAggregator : public DataReader {
   /// from the file name in BC.
   std::string BuildIDBinaryName;
 
-  /// Memory map info for a single file
+  /// Memory map info for a single file as recorded in perf.data
   struct MMapInfo {
-    uint64_t BaseAddress;
-    uint64_t Size;
-    uint64_t Offset;
-    int32_t PID{-1};
-    bool Forked{false};
-    uint64_t Time{0ULL}; // time in micro seconds
+    uint64_t BaseAddress{0}; /// Base address of the mapped binary.
+    uint64_t MMapAddress{0}; /// Address of the executable segment.
+    uint64_t Size{0};        /// Size of the mapping.
+    uint64_t Offset{0};      /// File offset of the mapped segment.
+    int32_t PID{-1};         /// Process ID.
+    bool Forked{false};      /// Was the process forked?
+    uint64_t Time{0ULL};     /// Time in micro seconds.
   };
 
   /// Per-PID map info for the binary
@@ -420,12 +421,8 @@ class DataAggregator : public DataReader {
   /// correspond to the binary allocated address space, are adjusted to avoid
   /// conflicts.
   void adjustAddress(uint64_t &Address, const MMapInfo &MMI) const {
-    if (Address >= MMI.BaseAddress && Address < MMI.BaseAddress + MMI.Size) {
-      // NOTE: Assumptions about the binary segment load table (PH for ELF)
-      //  Segment file offset equals virtual address (which is true for .so)
-      //  There aren't multiple executable segments loaded because MMapInfo
-      //  doesn't support them.
-      Address -= MMI.BaseAddress - MMI.Offset;
+    if (Address >= MMI.MMapAddress && Address < MMI.MMapAddress + MMI.Size) {
+      Address -= MMI.BaseAddress;
     } else if (Address < MMI.Size) {
       // Make sure the address is not treated as belonging to the binary.
       Address = (-1ULL);

bolt/include/bolt/Utils/BoltRevision.inc.in

@@ -1690,6 +1690,22 @@ void BinaryContext::printInstruction(raw_ostream &OS, const MCInst &Instruction,
   }
 }
 
+Optional<uint64_t>
+BinaryContext::getBaseAddressForMapping(uint64_t MMapAddress,
+                                        uint64_t FileOffset) const {
+  // Find a segment with a matching file offset.
+  for (auto &KV : SegmentMapInfo) {
+    const SegmentInfo &SegInfo = KV.second;
+    if (alignDown(SegInfo.FileOffset, SegInfo.Alignment) == FileOffset) {
+      // Use segment's aligned memory offset to calculate the base address.
+      const uint64_t MemOffset = alignDown(SegInfo.Address, SegInfo.Alignment);
+      return MMapAddress - MemOffset;
+    }
+  }
+
+  return NoneType();
+}
+
 ErrorOr<BinarySection &> BinaryContext::getSectionForAddress(uint64_t Address) {
   auto SI = AddressToSection.upper_bound(Address);
   if (SI != AddressToSection.begin()) {

bolt/lib/Core/BinaryContext.cpp

@@ -820,7 +820,8 @@ void DebugAbbrevWriter::addUnitAbbreviations(DWARFUnit &Unit) {
   auto hashAndAddAbbrev = [&](StringRef AbbrevData) -> bool {
     llvm::SHA1 Hasher;
     Hasher.update(AbbrevData);
-    StringRef Key = Hasher.final();
+    std::array<uint8_t, 20> Hash = Hasher.final();
+    StringRef Key((const char *)Hash.data(), Hash.size());
     auto Iter = AbbrevDataCache.find(Key);
     if (Iter != AbbrevDataCache.end()) {
       UnitsAbbrevData[&Unit] = Iter->second.get();

bolt/lib/Core/DebugData.cpp

@@ -168,16 +168,17 @@ bool skipRelocationProcessX86(uint64_t Type, uint64_t Contents) {
 bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   auto IsMov = [](uint64_t Contents) -> bool {
     // The bits 28-23 are 0b100101
-    if ((Contents & 0x1f800000) == 0x12800000)
-      return true;
-    return false;
+    return (Contents & 0x1f800000) == 0x12800000;
   };
 
   auto IsB = [](uint64_t Contents) -> bool {
     // The bits 31-26 are 0b000101
-    if ((Contents & 0xfc000000) == 0x14000000)
-      return true;
-    return false;
+    return (Contents & 0xfc000000) == 0x14000000;
+  };
+
+  auto IsAdr = [](uint64_t Contents) -> bool {
+    // The bits 31-24 are 0b0xx10000
+    return (Contents & 0x9f000000) == 0x10000000;
   };
 
   auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
@@ -205,7 +206,7 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   }
   }
 
-  // The ld might replace load/store instruction with jump and
+  // The linker might replace load/store instruction with jump and
   // veneer due to errata 843419
   // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
   // Thus load/store relocations for these instructions must be ignored
@@ -223,6 +224,18 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   }
   }
 
+  // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
+  switch (Type) {
+  default:
+    break;
+  case ELF::R_AARCH64_ADR_PREL_PG_HI21:
+  case ELF::R_AARCH64_ADD_ABS_LO12_NC:
+  case ELF::R_AARCH64_ADR_GOT_PAGE:
+  case ELF::R_AARCH64_LD64_GOT_LO12_NC:
+    if (IsAdr(Contents))
+      return true;
+  }
+
   return false;
 }
 

bolt/lib/Core/Relocation.cpp

@@ -1015,6 +1015,7 @@ uint64_t ShortenInstructions::shortenInstructions(BinaryFunction &Function) {
         continue;
 
       if (opts::Verbosity > 2) {
+        BC.scopeLock();
         outs() << "BOLT-INFO: shortening:\nBOLT-INFO:    ";
         BC.printInstruction(outs(), OriginalInst, 0, &Function);
         outs() << "BOLT-INFO: to:";

bolt/lib/Passes/BinaryPasses.cpp

@@ -1296,37 +1296,55 @@ std::error_code DataAggregator::printLBRHeatMap() {
   uint64_t NumTotalSamples = 0;
 
   while (hasData()) {
-    ErrorOr<PerfBranchSample> SampleRes = parseBranchSample();
-    if (std::error_code EC = SampleRes.getError()) {
-      if (EC == errc::no_such_process)
-        continue;
-      return EC;
-    }
-
-    PerfBranchSample &Sample = SampleRes.get();
+    if (opts::BasicAggregation) {
+      ErrorOr<PerfBasicSample> SampleRes = parseBasicSample();
+      if (std::error_code EC = SampleRes.getError()) {
+        if (EC == errc::no_such_process)
+          continue;
+        return EC;
+      }
+      PerfBasicSample &Sample = SampleRes.get();
+      HM.registerAddress(Sample.PC);
+      NumTotalSamples++;
+    } else {
+      ErrorOr<PerfBranchSample> SampleRes = parseBranchSample();
+      if (std::error_code EC = SampleRes.getError()) {
+        if (EC == errc::no_such_process)
+          continue;
+        return EC;
+      }
 
-    // LBRs are stored in reverse execution order. NextLBR refers to the next
-    // executed branch record.
-    const LBREntry *NextLBR = nullptr;
-    for (const LBREntry &LBR : Sample.LBR) {
-      if (NextLBR) {
-        // Record fall-through trace.
-        const uint64_t TraceFrom = LBR.To;
-        const uint64_t TraceTo = NextLBR->From;
-        ++FallthroughLBRs[Trace(TraceFrom, TraceTo)].InternCount;
+      PerfBranchSample &Sample = SampleRes.get();
+
+      // LBRs are stored in reverse execution order. NextLBR refers to the next
+      // executed branch record.
+      const LBREntry *NextLBR = nullptr;
+      for (const LBREntry &LBR : Sample.LBR) {
+        if (NextLBR) {
+          // Record fall-through trace.
+          const uint64_t TraceFrom = LBR.To;
+          const uint64_t TraceTo = NextLBR->From;
+          ++FallthroughLBRs[Trace(TraceFrom, TraceTo)].InternCount;
+        }
+        NextLBR = &LBR;
       }
-      NextLBR = &LBR;
-    }
-    if (!Sample.LBR.empty()) {
-      HM.registerAddress(Sample.LBR.front().To);
-      HM.registerAddress(Sample.LBR.back().From);
+      if (!Sample.LBR.empty()) {
+        HM.registerAddress(Sample.LBR.front().To);
+        HM.registerAddress(Sample.LBR.back().From);
+      }
+      NumTotalSamples += Sample.LBR.size();
     }
-    NumTotalSamples += Sample.LBR.size();
   }
 
   if (!NumTotalSamples) {
-    errs() << "HEATMAP-ERROR: no LBR traces detected in profile. "
-              "Cannot build heatmap.\n";
+    if (!opts::BasicAggregation) {
+      errs() << "HEATMAP-ERROR: no LBR traces detected in profile. "
+                "Cannot build heatmap. Use -nl for building heatmap from "
+                "basic events.\n";
+    } else {
+      errs() << "HEATMAP-ERROR: no samples detected in profile. "
+                "Cannot build heatmap.";
+    }
     exit(1);
   }
 
@@ -1925,7 +1943,7 @@ DataAggregator::parseMMapEvent() {
   }
 
   const StringRef BaseAddressStr = Line.split('[').second.split('(').first;
-  if (BaseAddressStr.getAsInteger(0, ParsedInfo.BaseAddress)) {
+  if (BaseAddressStr.getAsInteger(0, ParsedInfo.MMapAddress)) {
     reportError("expected base address");
     Diag << "Found: " << BaseAddressStr << "in '" << Line << "'\n";
     return make_error_code(llvm::errc::io_error);
@@ -1985,7 +2003,7 @@ std::error_code DataAggregator::parseMMapEvents() {
     dbgs() << "FileName -> mmap info:\n";
     for (const std::pair<const StringRef, MMapInfo> &Pair : GlobalMMapInfo)
       dbgs() << "  " << Pair.first << " : " << Pair.second.PID << " [0x"
-             << Twine::utohexstr(Pair.second.BaseAddress) << ", "
+             << Twine::utohexstr(Pair.second.MMapAddress) << ", "
              << Twine::utohexstr(Pair.second.Size) << " @ "
              << Twine::utohexstr(Pair.second.Offset) << "]\n";
   });
@@ -1999,26 +2017,42 @@ std::error_code DataAggregator::parseMMapEvents() {
 
   auto Range = GlobalMMapInfo.equal_range(NameToUse);
   for (auto I = Range.first; I != Range.second; ++I) {
-    const MMapInfo &MMapInfo = I->second;
-    if (BC->HasFixedLoadAddress && MMapInfo.BaseAddress) {
+    MMapInfo &MMapInfo = I->second;
+    if (BC->HasFixedLoadAddress && MMapInfo.MMapAddress) {
       // Check that the binary mapping matches one of the segments.
       bool MatchFound = false;
       for (auto &KV : BC->SegmentMapInfo) {
         SegmentInfo &SegInfo = KV.second;
-        // The mapping is page-aligned and hence the BaseAddress could be
+        // The mapping is page-aligned and hence the MMapAddress could be
         // different from the segment start address. We cannot know the page
         // size of the mapping, but we know it should not exceed the segment
         // alignment value. Hence we are performing an approximate check.
-        if (SegInfo.Address >= MMapInfo.BaseAddress &&
-            SegInfo.Address - MMapInfo.BaseAddress < SegInfo.Alignment) {
+        if (SegInfo.Address >= MMapInfo.MMapAddress &&
+            SegInfo.Address - MMapInfo.MMapAddress < SegInfo.Alignment) {
           MatchFound = true;
           break;
         }
       }
       if (!MatchFound) {
         errs() << "PERF2BOLT-WARNING: ignoring mapping of " << NameToUse
-               << " at 0x" << Twine::utohexstr(MMapInfo.BaseAddress) << '\n';
+               << " at 0x" << Twine::utohexstr(MMapInfo.MMapAddress) << '\n';
+        continue;
+      }
+    }
+
+    // Set base address for shared objects.
+    if (!BC->HasFixedLoadAddress) {
+      Optional<uint64_t> BaseAddress =
+          BC->getBaseAddressForMapping(MMapInfo.MMapAddress, MMapInfo.Offset);
+      if (!BaseAddress) {
+        errs() << "PERF2BOLT-WARNING: unable to find base address of the "
+                  "binary when memory mapped at 0x"
+               << Twine::utohexstr(MMapInfo.MMapAddress)
+               << " using file offset 0x" << Twine::utohexstr(MMapInfo.Offset)
+               << ". Ignoring profile data for this mapping\n";
         continue;
+      } else {
+        MMapInfo.BaseAddress = *BaseAddress;
       }
     }
 
@@ -2092,7 +2126,7 @@ std::error_code DataAggregator::parseTaskEvents() {
   LLVM_DEBUG({
     for (std::pair<const uint64_t, MMapInfo> &MMI : BinaryMMapInfo)
       outs() << "  " << MMI.second.PID << (MMI.second.Forked ? " (forked)" : "")
-             << ": (0x" << Twine::utohexstr(MMI.second.BaseAddress) << ": 0x"
+             << ": (0x" << Twine::utohexstr(MMI.second.MMapAddress) << ": 0x"
              << Twine::utohexstr(MMI.second.Size) << ")\n";
   });