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arsenmarsenm
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Transforms: Fix code duplication between LowerAtomic and AtomicExpand
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5 files changed

+80
-121
lines changed

5 files changed

+80
-121
lines changed

‎llvm/include/llvm/Transforms/Utils/LowerAtomic.h

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,11 @@
1414
#ifndef LLVM_TRANSFORMS_SCALAR_LOWERATOMIC_H
1515
#define LLVM_TRANSFORMS_SCALAR_LOWERATOMIC_H
1616

17+
#include "llvm/IR/Instructions.h"
18+
1719
namespace llvm {
18-
class AtomicCmpXchgInst;
19-
class AtomicRMWInst;
20+
21+
class IRBuilderBase;
2022

2123
/// Convert the given Cmpxchg into primitive load and compare.
2224
bool lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI);
@@ -25,6 +27,11 @@ bool lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI);
2527
/// assuming that doing so is legal. Return true if the lowering
2628
/// succeeds.
2729
bool lowerAtomicRMWInst(AtomicRMWInst *RMWI);
30+
31+
/// Emit IR to implement the given atomicrmw operation on values in registers,
32+
/// returning the new value.
33+
Value *buildAtomicRMWValue(AtomicRMWInst::BinOp Op, IRBuilderBase &Builder,
34+
Value *Loaded, Value *Inc);
2835
}
2936

3037
#endif // LLVM_TRANSFORMS_SCALAR_LOWERATOMIC_H

‎llvm/lib/CodeGen/AtomicExpandPass.cpp

Lines changed: 6 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -544,47 +544,6 @@ static void createCmpXchgInstFun(IRBuilder<> &Builder, Value *Addr,
544544
NewLoaded = Builder.CreateBitCast(NewLoaded, OrigTy);
545545
}
546546

547-
/// Emit IR to implement the given atomicrmw operation on values in registers,
548-
/// returning the new value.
549-
static Value *performAtomicOp(AtomicRMWInst::BinOp Op, IRBuilder<> &Builder,
550-
Value *Loaded, Value *Inc) {
551-
Value *NewVal;
552-
switch (Op) {
553-
case AtomicRMWInst::Xchg:
554-
return Inc;
555-
case AtomicRMWInst::Add:
556-
return Builder.CreateAdd(Loaded, Inc, "new");
557-
case AtomicRMWInst::Sub:
558-
return Builder.CreateSub(Loaded, Inc, "new");
559-
case AtomicRMWInst::And:
560-
return Builder.CreateAnd(Loaded, Inc, "new");
561-
case AtomicRMWInst::Nand:
562-
return Builder.CreateNot(Builder.CreateAnd(Loaded, Inc), "new");
563-
case AtomicRMWInst::Or:
564-
return Builder.CreateOr(Loaded, Inc, "new");
565-
case AtomicRMWInst::Xor:
566-
return Builder.CreateXor(Loaded, Inc, "new");
567-
case AtomicRMWInst::Max:
568-
NewVal = Builder.CreateICmpSGT(Loaded, Inc);
569-
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
570-
case AtomicRMWInst::Min:
571-
NewVal = Builder.CreateICmpSLE(Loaded, Inc);
572-
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
573-
case AtomicRMWInst::UMax:
574-
NewVal = Builder.CreateICmpUGT(Loaded, Inc);
575-
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
576-
case AtomicRMWInst::UMin:
577-
NewVal = Builder.CreateICmpULE(Loaded, Inc);
578-
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
579-
case AtomicRMWInst::FAdd:
580-
return Builder.CreateFAdd(Loaded, Inc, "new");
581-
case AtomicRMWInst::FSub:
582-
return Builder.CreateFSub(Loaded, Inc, "new");
583-
default:
584-
llvm_unreachable("Unknown atomic op");
585-
}
586-
}
587-
588547
bool AtomicExpand::tryExpandAtomicRMW(AtomicRMWInst *AI) {
589548
LLVMContext &Ctx = AI->getModule()->getContext();
590549
TargetLowering::AtomicExpansionKind Kind = TLI->shouldExpandAtomicRMWInIR(AI);
@@ -599,8 +558,8 @@ bool AtomicExpand::tryExpandAtomicRMW(AtomicRMWInst *AI) {
599558
TargetLoweringBase::AtomicExpansionKind::LLSC);
600559
} else {
601560
auto PerformOp = [&](IRBuilder<> &Builder, Value *Loaded) {
602-
return performAtomicOp(AI->getOperation(), Builder, Loaded,
603-
AI->getValOperand());
561+
return buildAtomicRMWValue(AI->getOperation(), Builder, Loaded,
562+
AI->getValOperand());
604563
};
605564
expandAtomicOpToLLSC(AI, AI->getType(), AI->getPointerOperand(),
606565
AI->getAlign(), AI->getOrdering(), PerformOp);
@@ -810,7 +769,7 @@ static Value *performMaskedAtomicOp(AtomicRMWInst::BinOp Op,
810769
case AtomicRMWInst::Sub:
811770
case AtomicRMWInst::Nand: {
812771
// The other arithmetic ops need to be masked into place.
813-
Value *NewVal = performAtomicOp(Op, Builder, Loaded, Shifted_Inc);
772+
Value *NewVal = buildAtomicRMWValue(Op, Builder, Loaded, Shifted_Inc);
814773
Value *NewVal_Masked = Builder.CreateAnd(NewVal, PMV.Mask);
815774
Value *Loaded_MaskOut = Builder.CreateAnd(Loaded, PMV.Inv_Mask);
816775
Value *FinalVal = Builder.CreateOr(Loaded_MaskOut, NewVal_Masked);
@@ -824,7 +783,7 @@ static Value *performMaskedAtomicOp(AtomicRMWInst::BinOp Op,
824783
// truncate down to the original size, and expand out again after
825784
// doing the operation.
826785
Value *Loaded_Extract = extractMaskedValue(Builder, Loaded, PMV);
827-
Value *NewVal = performAtomicOp(Op, Builder, Loaded_Extract, Inc);
786+
Value *NewVal = buildAtomicRMWValue(Op, Builder, Loaded_Extract, Inc);
828787
Value *FinalVal = insertMaskedValue(Builder, Loaded, NewVal, PMV);
829788
return FinalVal;
830789
}
@@ -1558,8 +1517,8 @@ bool llvm::expandAtomicRMWToCmpXchg(AtomicRMWInst *AI,
15581517
Builder, AI->getType(), AI->getPointerOperand(), AI->getAlign(),
15591518
AI->getOrdering(), AI->getSyncScopeID(),
15601519
[&](IRBuilder<> &Builder, Value *Loaded) {
1561-
return performAtomicOp(AI->getOperation(), Builder, Loaded,
1562-
AI->getValOperand());
1520+
return buildAtomicRMWValue(AI->getOperation(), Builder, Loaded,
1521+
AI->getValOperand());
15631522
},
15641523
CreateCmpXchg);
15651524

‎llvm/lib/Transforms/Utils/LowerAtomic.cpp

Lines changed: 33 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -39,60 +39,53 @@ bool llvm::lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
3939
return true;
4040
}
4141

42-
bool llvm::lowerAtomicRMWInst(AtomicRMWInst *RMWI) {
43-
IRBuilder<> Builder(RMWI);
44-
Value *Ptr = RMWI->getPointerOperand();
45-
Value *Val = RMWI->getValOperand();
46-
47-
LoadInst *Orig = Builder.CreateLoad(Val->getType(), Ptr);
48-
Value *Res = nullptr;
49-
50-
switch (RMWI->getOperation()) {
51-
default: llvm_unreachable("Unexpected RMW operation");
42+
Value *llvm::buildAtomicRMWValue(AtomicRMWInst::BinOp Op,
43+
IRBuilderBase &Builder, Value *Loaded,
44+
Value *Inc) {
45+
Value *NewVal;
46+
switch (Op) {
5247
case AtomicRMWInst::Xchg:
53-
Res = Val;
54-
break;
48+
return Inc;
5549
case AtomicRMWInst::Add:
56-
Res = Builder.CreateAdd(Orig, Val);
57-
break;
50+
return Builder.CreateAdd(Loaded, Inc, "new");
5851
case AtomicRMWInst::Sub:
59-
Res = Builder.CreateSub(Orig, Val);
60-
break;
52+
return Builder.CreateSub(Loaded, Inc, "new");
6153
case AtomicRMWInst::And:
62-
Res = Builder.CreateAnd(Orig, Val);
63-
break;
54+
return Builder.CreateAnd(Loaded, Inc, "new");
6455
case AtomicRMWInst::Nand:
65-
Res = Builder.CreateNot(Builder.CreateAnd(Orig, Val));
66-
break;
56+
return Builder.CreateNot(Builder.CreateAnd(Loaded, Inc), "new");
6757
case AtomicRMWInst::Or:
68-
Res = Builder.CreateOr(Orig, Val);
69-
break;
58+
return Builder.CreateOr(Loaded, Inc, "new");
7059
case AtomicRMWInst::Xor:
71-
Res = Builder.CreateXor(Orig, Val);
72-
break;
60+
return Builder.CreateXor(Loaded, Inc, "new");
7361
case AtomicRMWInst::Max:
74-
Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
75-
Val, Orig);
76-
break;
62+
NewVal = Builder.CreateICmpSGT(Loaded, Inc);
63+
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
7764
case AtomicRMWInst::Min:
78-
Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
79-
Orig, Val);
80-
break;
65+
NewVal = Builder.CreateICmpSLE(Loaded, Inc);
66+
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
8167
case AtomicRMWInst::UMax:
82-
Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
83-
Val, Orig);
84-
break;
68+
NewVal = Builder.CreateICmpUGT(Loaded, Inc);
69+
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
8570
case AtomicRMWInst::UMin:
86-
Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
87-
Orig, Val);
88-
break;
71+
NewVal = Builder.CreateICmpULE(Loaded, Inc);
72+
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
8973
case AtomicRMWInst::FAdd:
90-
Res = Builder.CreateFAdd(Orig, Val);
91-
break;
74+
return Builder.CreateFAdd(Loaded, Inc, "new");
9275
case AtomicRMWInst::FSub:
93-
Res = Builder.CreateFSub(Orig, Val);
94-
break;
76+
return Builder.CreateFSub(Loaded, Inc, "new");
77+
default:
78+
llvm_unreachable("Unknown atomic op");
9579
}
80+
}
81+
82+
bool llvm::lowerAtomicRMWInst(AtomicRMWInst *RMWI) {
83+
IRBuilder<> Builder(RMWI);
84+
Value *Ptr = RMWI->getPointerOperand();
85+
Value *Val = RMWI->getValOperand();
86+
87+
LoadInst *Orig = Builder.CreateLoad(Val->getType(), Ptr);
88+
Value *Res = buildAtomicRMWValue(RMWI->getOperation(), Builder, Orig, Val);
9689
Builder.CreateStore(Res, Ptr);
9790
RMWI->replaceAllUsesWith(Orig);
9891
RMWI->eraseFromParent();

‎llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -196,8 +196,8 @@ define i32 @atomicrmw_xchg_private_i32(i32 addrspace(5)* %ptr) {
196196
define i32 @atomicrmw_add_private_i32(i32 addrspace(5)* %ptr) {
197197
; IR-LABEL: @atomicrmw_add_private_i32(
198198
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
199-
; IR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 4
200-
; IR-NEXT: store i32 [[TMP2]], i32 addrspace(5)* [[PTR]], align 4
199+
; IR-NEXT: [[NEW:%.*]] = add i32 [[TMP1]], 4
200+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
201201
; IR-NEXT: ret i32 [[TMP1]]
202202
;
203203
; GCN-LABEL: atomicrmw_add_private_i32:
@@ -217,8 +217,8 @@ define i32 @atomicrmw_add_private_i32(i32 addrspace(5)* %ptr) {
217217
define i32 @atomicrmw_sub_private_i32(i32 addrspace(5)* %ptr) {
218218
; IR-LABEL: @atomicrmw_sub_private_i32(
219219
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
220-
; IR-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 4
221-
; IR-NEXT: store i32 [[TMP2]], i32 addrspace(5)* [[PTR]], align 4
220+
; IR-NEXT: [[NEW:%.*]] = sub i32 [[TMP1]], 4
221+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
222222
; IR-NEXT: ret i32 [[TMP1]]
223223
;
224224
; GCN-LABEL: atomicrmw_sub_private_i32:
@@ -238,8 +238,8 @@ define i32 @atomicrmw_sub_private_i32(i32 addrspace(5)* %ptr) {
238238
define i32 @atomicrmw_and_private_i32(i32 addrspace(5)* %ptr) {
239239
; IR-LABEL: @atomicrmw_and_private_i32(
240240
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
241-
; IR-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 4
242-
; IR-NEXT: store i32 [[TMP2]], i32 addrspace(5)* [[PTR]], align 4
241+
; IR-NEXT: [[NEW:%.*]] = and i32 [[TMP1]], 4
242+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
243243
; IR-NEXT: ret i32 [[TMP1]]
244244
;
245245
; GCN-LABEL: atomicrmw_and_private_i32:
@@ -260,8 +260,8 @@ define i32 @atomicrmw_nand_private_i32(i32 addrspace(5)* %ptr) {
260260
; IR-LABEL: @atomicrmw_nand_private_i32(
261261
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
262262
; IR-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 4
263-
; IR-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
264-
; IR-NEXT: store i32 [[TMP3]], i32 addrspace(5)* [[PTR]], align 4
263+
; IR-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1
264+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
265265
; IR-NEXT: ret i32 [[TMP1]]
266266
;
267267
; GCN-LABEL: atomicrmw_nand_private_i32:
@@ -282,8 +282,8 @@ define i32 @atomicrmw_nand_private_i32(i32 addrspace(5)* %ptr) {
282282
define i32 @atomicrmw_or_private_i32(i32 addrspace(5)* %ptr) {
283283
; IR-LABEL: @atomicrmw_or_private_i32(
284284
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
285-
; IR-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 4
286-
; IR-NEXT: store i32 [[TMP2]], i32 addrspace(5)* [[PTR]], align 4
285+
; IR-NEXT: [[NEW:%.*]] = or i32 [[TMP1]], 4
286+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
287287
; IR-NEXT: ret i32 [[TMP1]]
288288
;
289289
; GCN-LABEL: atomicrmw_or_private_i32:
@@ -303,8 +303,8 @@ define i32 @atomicrmw_or_private_i32(i32 addrspace(5)* %ptr) {
303303
define i32 @atomicrmw_xor_private_i32(i32 addrspace(5)* %ptr) {
304304
; IR-LABEL: @atomicrmw_xor_private_i32(
305305
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
306-
; IR-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 4
307-
; IR-NEXT: store i32 [[TMP2]], i32 addrspace(5)* [[PTR]], align 4
306+
; IR-NEXT: [[NEW:%.*]] = xor i32 [[TMP1]], 4
307+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
308308
; IR-NEXT: ret i32 [[TMP1]]
309309
;
310310
; GCN-LABEL: atomicrmw_xor_private_i32:
@@ -324,9 +324,9 @@ define i32 @atomicrmw_xor_private_i32(i32 addrspace(5)* %ptr) {
324324
define i32 @atomicrmw_max_private_i32(i32 addrspace(5)* %ptr) {
325325
; IR-LABEL: @atomicrmw_max_private_i32(
326326
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
327-
; IR-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 4
328-
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 4, i32 [[TMP1]]
329-
; IR-NEXT: store i32 [[TMP3]], i32 addrspace(5)* [[PTR]], align 4
327+
; IR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], 4
328+
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
329+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
330330
; IR-NEXT: ret i32 [[TMP1]]
331331
;
332332
; GCN-LABEL: atomicrmw_max_private_i32:
@@ -346,9 +346,9 @@ define i32 @atomicrmw_max_private_i32(i32 addrspace(5)* %ptr) {
346346
define i32 @atomicrmw_min_private_i32(i32 addrspace(5)* %ptr) {
347347
; IR-LABEL: @atomicrmw_min_private_i32(
348348
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
349-
; IR-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 4
350-
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
351-
; IR-NEXT: store i32 [[TMP3]], i32 addrspace(5)* [[PTR]], align 4
349+
; IR-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 4
350+
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
351+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
352352
; IR-NEXT: ret i32 [[TMP1]]
353353
;
354354
; GCN-LABEL: atomicrmw_min_private_i32:
@@ -368,9 +368,9 @@ define i32 @atomicrmw_min_private_i32(i32 addrspace(5)* %ptr) {
368368
define i32 @atomicrmw_umax_private_i32(i32 addrspace(5)* %ptr) {
369369
; IR-LABEL: @atomicrmw_umax_private_i32(
370370
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
371-
; IR-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 4
372-
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 4, i32 [[TMP1]]
373-
; IR-NEXT: store i32 [[TMP3]], i32 addrspace(5)* [[PTR]], align 4
371+
; IR-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], 4
372+
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
373+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
374374
; IR-NEXT: ret i32 [[TMP1]]
375375
;
376376
; GCN-LABEL: atomicrmw_umax_private_i32:
@@ -390,9 +390,9 @@ define i32 @atomicrmw_umax_private_i32(i32 addrspace(5)* %ptr) {
390390
define i32 @atomicrmw_umin_private_i32(i32 addrspace(5)* %ptr) {
391391
; IR-LABEL: @atomicrmw_umin_private_i32(
392392
; IR-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(5)* [[PTR:%.*]], align 4
393-
; IR-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 4
394-
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
395-
; IR-NEXT: store i32 [[TMP3]], i32 addrspace(5)* [[PTR]], align 4
393+
; IR-NEXT: [[TMP2:%.*]] = icmp ule i32 [[TMP1]], 4
394+
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
395+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[PTR]], align 4
396396
; IR-NEXT: ret i32 [[TMP1]]
397397
;
398398
; GCN-LABEL: atomicrmw_umin_private_i32:
@@ -412,8 +412,8 @@ define i32 @atomicrmw_umin_private_i32(i32 addrspace(5)* %ptr) {
412412
define float @atomicrmw_fadd_private_i32(float addrspace(5)* %ptr) {
413413
; IR-LABEL: @atomicrmw_fadd_private_i32(
414414
; IR-NEXT: [[TMP1:%.*]] = load float, float addrspace(5)* [[PTR:%.*]], align 4
415-
; IR-NEXT: [[TMP2:%.*]] = fadd float [[TMP1]], 2.000000e+00
416-
; IR-NEXT: store float [[TMP2]], float addrspace(5)* [[PTR]], align 4
415+
; IR-NEXT: [[NEW:%.*]] = fadd float [[TMP1]], 2.000000e+00
416+
; IR-NEXT: store float [[NEW]], float addrspace(5)* [[PTR]], align 4
417417
; IR-NEXT: ret float [[TMP1]]
418418
;
419419
; GCN-LABEL: atomicrmw_fadd_private_i32:
@@ -433,8 +433,8 @@ define float @atomicrmw_fadd_private_i32(float addrspace(5)* %ptr) {
433433
define float @atomicrmw_fsub_private_i32(float addrspace(5)* %ptr, float %val) {
434434
; IR-LABEL: @atomicrmw_fsub_private_i32(
435435
; IR-NEXT: [[TMP1:%.*]] = load float, float addrspace(5)* [[PTR:%.*]], align 4
436-
; IR-NEXT: [[TMP2:%.*]] = fsub float [[TMP1]], [[VAL:%.*]]
437-
; IR-NEXT: store float [[TMP2]], float addrspace(5)* [[PTR]], align 4
436+
; IR-NEXT: [[NEW:%.*]] = fsub float [[TMP1]], [[VAL:%.*]]
437+
; IR-NEXT: store float [[NEW]], float addrspace(5)* [[PTR]], align 4
438438
; IR-NEXT: ret float [[TMP1]]
439439
;
440440
; GCN-LABEL: atomicrmw_fsub_private_i32:
@@ -461,8 +461,8 @@ define amdgpu_kernel void @alloca_promote_atomicrmw_private_lds_promote(i32 addr
461461
; IR-NEXT: store i32 1, i32 addrspace(5)* [[GEP2]], align 4
462462
; IR-NEXT: [[GEP3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* [[TMP]], i32 0, i32 [[IN:%.*]]
463463
; IR-NEXT: [[TMP0:%.*]] = load i32, i32 addrspace(5)* [[GEP3]], align 4
464-
; IR-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 7
465-
; IR-NEXT: store i32 [[TMP1]], i32 addrspace(5)* [[GEP3]], align 4
464+
; IR-NEXT: [[NEW:%.*]] = add i32 [[TMP0]], 7
465+
; IR-NEXT: store i32 [[NEW]], i32 addrspace(5)* [[GEP3]], align 4
466466
; IR-NEXT: store i32 [[TMP0]], i32 addrspace(1)* [[OUT:%.*]], align 4
467467
; IR-NEXT: ret void
468468
;

‎llvm/test/CodeGen/NVPTX/atomic-lower-local.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ define double @kernel(double addrspace(5)* %ptr, double %val) {
1111
%res = atomicrmw fadd double addrspace(5)* %ptr, double %val monotonic, align 8
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ret double %res
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; CHECK: %1 = load double, double addrspace(5)* %ptr, align 8
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; CHECK-NEXT: %2 = fadd double %1, %val
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; CHECK-NEXT: store double %2, double addrspace(5)* %ptr, align 8
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; CHECK-NEXT: %new = fadd double %1, %val
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; CHECK-NEXT: store double %new, double addrspace(5)* %ptr, align 8
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; CHECK-NEXT: ret double %1
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}
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